rs6000: call vector load/store with length only on 64-bit Power10

gcc/
	PR target/96762
	* config/rs6000/rs6000-string.c (expand_block_move): Call vector
	load/store with length only on 64-bit Power10.

gcc/testsuite/
	PR target/96762
	* gcc.target/powerpc/pr96762.c: New.

(cherry picked from commit 946b8967b905257ac9f140225db744c9a6ab91be)

diff --git a/gcc/config/rs6000/rs6000-string.c b/gcc/config/rs6000/rs6000-string.c
index cc75ca5848e254eb41a95ebb0127d8237024808f..b7c77372c70bf60e76fe3098c8fc7219d95a1e63 100644 (file)
--- a/gcc/config/rs6000/rs6000-string.c
+++ b/gcc/config/rs6000/rs6000-string.c
@@ -2811,11 +2811,17 @@ expand_block_move (rtx operands[], bool might_overlap)
          gen_func.mov = gen_vsx_movv2di_64bit;
        }
       else if (TARGET_BLOCK_OPS_UNALIGNED_VSX
-              && TARGET_POWER10 && bytes < 16
+              /* Only use lxvl/stxvl on 64bit POWER10.  */
+              && TARGET_POWER10
+              && TARGET_64BIT
+              && bytes < 16
               && orig_bytes > 16
-              && !(bytes == 1 || bytes == 2
-                   || bytes == 4 || bytes == 8)
-              && (align >= 128 || !STRICT_ALIGNMENT))
+              && !(bytes == 1
+                   || bytes == 2
+                   || bytes == 4
+                   || bytes == 8)
+              && (align >= 128
+                  || !STRICT_ALIGNMENT))
        {
          /* Only use lxvl/stxvl if it could replace multiple ordinary
             loads+stores.  Also don't use it unless we likely already

diff --git a/gcc/testsuite/gcc.target/powerpc/pr96762.c b/gcc/testsuite/gcc.target/powerpc/pr96762.c
new file mode 100644 (file)
index 0000000..a59deb4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr96762.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Verify there is no ICE on ilp32 env.  */
+
+extern void foo (char *);
+
+void
+bar (void)
+{
+  char zj[] = "XXXXXXXXXXXXXXXX";
+  foo (zj);
+}