drm/ast: Align Gen1 DVO detection to register manual

Align variable names and register constants for TX-chip detection
to the names in the register manual.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250117103450.28692-7-tzimmermann@suse.de

diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
index 50b57bc15d53c719c7f2db6b4c93b55f844d268f..40d3b7770cf18d5b9659e9d720d5dd0ac84d3c43 100644 (file)
--- a/drivers/gpu/drm/ast/ast_main.c
+++ b/drivers/gpu/drm/ast/ast_main.c
@@ -76,7 +76,7 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
        };
 
        struct drm_device *dev = &ast->base;
-       u8 jreg, vgacrd1;
+       u8 vgacra3, vgacrd1;
 
        /*
         * Several of the listed TX chips are not explicitly supported
@@ -106,8 +106,8 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
                 * SIL164 when there is none.
                 */
                if (!need_post) {
-                       jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
-                       if (jreg & 0x80)
+                       vgacra3 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
+                       if (vgacra3 & AST_IO_VGACRA3_DVO_ENABLED)
                                ast->tx_chip = AST_TX_SIL164;
                }
        } else if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) {

diff --git a/drivers/gpu/drm/ast/ast_reg.h b/drivers/gpu/drm/ast/ast_reg.h
index 2aadf07d135afadcaa57f23d3c74bbb38eb437ae..0745d58e5b4507abb55846b6d91ad2e8188f22cc 100644 (file)
--- a/drivers/gpu/drm/ast/ast_reg.h
+++ b/drivers/gpu/drm/ast/ast_reg.h
@@ -32,6 +32,7 @@
 #define AST_IO_VGACR80_PASSWORD                (0xa8)
 #define AST_IO_VGACRA1_VGAIO_DISABLED  BIT(1)
 #define AST_IO_VGACRA1_MMIO_ENABLED    BIT(2)
+#define AST_IO_VGACRA3_DVO_ENABLED     BIT(7)
 #define AST_IO_VGACRB6_HSYNC_OFF       BIT(0)
 #define AST_IO_VGACRB6_VSYNC_OFF       BIT(1)
 #define AST_IO_VGACRCB_HWC_16BPP       BIT(0) /* set: ARGB4444, cleared: 2bpp palette */