dev_dbg(dev, "pixel rate on CSI-2 bus:\t%u\n",
pll->pixel_rate_csi);
- dev_dbg(dev, "flags%s%s%s%s%s%s%s%s%s%s\n",
+ dev_dbg(dev, "flags%s%s%s%s%s%s%s%s%s%s%s\n",
pll->flags & PLL_FL(OP_PIX_CLOCK_PER_LANE) ? " op-pix-clock-per-lane" : "",
pll->flags & PLL_FL(NO_OP_CLOCKS) ? " no-op-clocks" : "",
+ pll->flags & PLL_FL(EVEN_PLL_MULTIPLIER) ? " even-pll-multiplier" : "",
pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "",
pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ?
" ext-ip-pll-divider" : "",
more_mul *= DIV_ROUND_UP(lim_fr->min_pll_multiplier, mul * more_mul);
dev_dbg(dev, "more_mul2: %u\n", more_mul);
+ if (pll->flags & CCS_PLL_FLAG_EVEN_PLL_MULTIPLIER &&
+ (mul & 1) && (more_mul & 1))
+ more_mul <<= 1;
+
pll_fr->pll_multiplier = mul * more_mul;
if (pll_fr->pll_multiplier > lim_fr->max_pll_multiplier) {
dev_dbg(dev, "pll multiplier %u too high\n",
if (!is_one_or_even(i))
i <<= 1;
+ if (pll->flags & CCS_PLL_FLAG_EVEN_PLL_MULTIPLIER &&
+ mul & 1 && i & 1)
+ i <<= 1;
+
dev_dbg(dev, "final more_mul: %u\n", i);
if (i > more_mul_max) {
dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max);
/* op pix clock is for all lanes in total normally */
#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0)
#define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1)
+#define CCS_PLL_FLAG_EVEN_PLL_MULTIPLIER BIT(3)
/* CCS PLL flags */
#define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2)
#define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4)