arm64: dts: qcom: ipq9574: Enable SPI NAND for ipq9574

Enable SPI NAND support for ipq9574 SoC.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Link: https://lore.kernel.org/r/20250306113357.126602-3-quic_mdalam@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
index ae12f069f26fa53ae15657d5fa2ee297e68c3ec8..140e989712b21115e20dd93703c197074c24884f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
@@ -139,6 +139,50 @@
                drive-strength = <8>;
                bias-pull-up;
        };
+
+       qpic_snand_default_state: qpic-snand-default-state {
+               clock-pins {
+                       pins = "gpio5";
+                       function = "qspi_clk";
+                       drive-strength = <8>;
+                       bias-disable;
+               };
+
+               cs-pins {
+                       pins = "gpio4";
+                       function = "qspi_cs";
+                       drive-strength = <8>;
+                       bias-disable;
+               };
+
+               data-pins {
+                       pins = "gpio0", "gpio1", "gpio2", "gpio3";
+                       function = "qspi_data";
+                       drive-strength = <8>;
+                       bias-disable;
+               };
+       };
+};
+
+&qpic_bam {
+       status = "okay";
+};
+
+&qpic_nand {
+       pinctrl-0 = <&qpic_snand_default_state>;
+       pinctrl-names = "default";
+
+       status = "okay";
+
+       flash@0 {
+               compatible = "spi-nand";
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               nand-ecc-engine = <&qpic_nand>;
+               nand-ecc-strength = <4>;
+               nand-ecc-step-size = <512>;
+       };
 };
 
 &usb_0_dwc3 {