arm64: dts: imx8mq: Add Root Port node and PERST property

Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and add the reset-gpios property in Root
Port.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index d48f901487d49ac94cf51fdcc7df718e3a0915bd..e7d87ea81b697ebfcc13e7bf460a4adbbe94d4af 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -369,6 +369,7 @@
 &pcie0 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
+       /* This property is deprecated, use reset-gpios from the Root Port node. */
        reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
        clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
                 <&pcie0_refclk>,
@@ -389,9 +390,14 @@
        status = "disabled";
 };
 
+&pcie0_port0 {
+       reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
+};
+
 &pcie1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie1>;
+       /* This property is deprecated, use reset-gpios from the Root Port node. */
        reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
        clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
                 <&pcie0_refclk>,
@@ -414,6 +420,10 @@
        status = "disabled";
 };
 
+&pcie1_port0 {
+       reset-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
+};
+
 &pgc_gpu {
        power-supply = <&sw1a_reg>;
 };

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 6a25e219832cedaaaf1b89acd3eb6f35a2698bf2..e60872aeeb49eeb583028890655ca2769f5cea4c 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1768,6 +1768,17 @@
                        assigned-clock-rates = <250000000>, <100000000>,
                                               <10000000>;
                        status = "disabled";
+
+                       pcie0_port0: pcie@0 {
+                               compatible = "pciclass,0604";
+                               device_type = "pci";
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               bus-range = <0x01 0xff>;
+
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               ranges;
+                       };
                };
 
                pcie0_ep: pcie-ep@33800000 {
@@ -1846,6 +1857,17 @@
                        assigned-clock-rates = <250000000>, <100000000>,
                                               <10000000>;
                        status = "disabled";
+
+                       pcie1_port0: pcie@0 {
+                               compatible = "pciclass,0604";
+                               device_type = "pci";
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               bus-range = <0x01 0xff>;
+
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               ranges;
+                       };
                };
 
                pcie1_ep: pcie-ep@33c00000 {