*/
#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
#include <dt-bindings/clock/qcom,rpmh.h>
port@0 {
reg = <0>;
+
mdss0_intf0_out: endpoint {
remote-endpoint = <&mdss0_dp0_in>;
};
};
+ port@1 {
+ reg = <1>;
+
+ mdss0_intf1_out: endpoint {
+ remote-endpoint = <&mdss0_dsi0_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ mdss0_intf2_out: endpoint {
+ remote-endpoint = <&mdss0_dsi1_in>;
+ };
+ };
+
port@4 {
reg = <4>;
+
mdss0_intf4_out: endpoint {
remote-endpoint = <&mdss0_dp1_in>;
};
port@5 {
reg = <5>;
+
mdss0_intf5_out: endpoint {
remote-endpoint = <&mdss0_dp3_in>;
};
port@6 {
reg = <6>;
+
mdss0_intf6_out: endpoint {
remote-endpoint = <&mdss0_dp2_in>;
};
};
};
+ mdss0_dsi0: dsi@ae94000 {
+ compatible = "qcom,sc8280xp-dsi-ctrl",
+ "qcom,sa8775p-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae94000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss0>;
+ interrupts = <4>;
+
+ clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc0 DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc0 DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ refgen-supply = <&refgen>;
+
+ phys = <&mdss0_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss0_dsi0_in: endpoint {
+ remote-endpoint = <&mdss0_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss0_dsi0_out: endpoint {
+ };
+ };
+ };
+
+ dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ mdss0_dsi0_phy: phy@ae94400 {
+ compatible = "qcom,sc8280xp-dsi-phy-5nm",
+ "qcom,sa8775p-dsi-phy-5nm";
+ reg = <0 0x0ae94400 0 0x200>,
+ <0 0x0ae94600 0 0x280>,
+ <0 0x0ae94900 0 0x280>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
+ mdss0_dsi1: dsi@ae96000 {
+ compatible = "qcom,sc8280xp-dsi-ctrl",
+ "qcom,sa8775p-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae96000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss0>;
+ interrupts = <5>;
+
+ clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK>,
+ <&dispcc0 DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&dispcc0 DISP_CC_MDSS_PCLK1_CLK>,
+ <&dispcc0 DISP_CC_MDSS_ESC1_CLK>,
+ <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK_SRC>,
+ <&dispcc0 DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ refgen-supply = <&refgen>;
+
+ phys = <&mdss0_dsi1_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss0_dsi1_in: endpoint {
+ remote-endpoint = <&mdss0_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss0_dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss0_dsi1_phy: phy@ae96400 {
+ compatible = "qcom,sc8280xp-dsi-phy-5nm",
+ "qcom,sa8775p-dsi-phy-5nm";
+ reg = <0 0x0ae96400 0 0x200>,
+ <0 0x0ae96600 0 0x280>,
+ <0 0x0ae96900 0 0x280>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
mdss0_dp1: displayport-controller@ae98000 {
compatible = "qcom,sc8280xp-dp";
reg = <0 0xae98000 0 0x200>,
<&mdss0_dp2_phy 1>,
<&mdss0_dp3_phy 0>,
<&mdss0_dp3_phy 1>,
- <0>,
- <0>,
- <0>,
- <0>;
+ <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>,
+ <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>;
power-domains = <&rpmhpd SC8280XP_MMCX>;
#clock-cells = <1>;
port@0 {
reg = <0>;
+
mdss1_intf0_out: endpoint {
remote-endpoint = <&mdss1_dp0_in>;
};
};
+ port@1 {
+ reg = <1>;
+
+ mdss1_intf1_out: endpoint {
+ remote-endpoint = <&mdss1_dsi0_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ mdss1_intf2_out: endpoint {
+ remote-endpoint = <&mdss1_dsi1_in>;
+ };
+ };
+
port@4 {
reg = <4>;
+
mdss1_intf4_out: endpoint {
remote-endpoint = <&mdss1_dp1_in>;
};
port@5 {
reg = <5>;
+
mdss1_intf5_out: endpoint {
remote-endpoint = <&mdss1_dp3_in>;
};
port@6 {
reg = <6>;
+
mdss1_intf6_out: endpoint {
remote-endpoint = <&mdss1_dp2_in>;
};
};
};
+ mdss1_dsi0: dsi@22094000 {
+ compatible = "qcom,sc8280xp-dsi-ctrl",
+ "qcom,sa8775p-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0 0x22094000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss1>;
+ interrupts = <4>;
+
+ clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc1 DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc1 DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc1 DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc1 DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ refgen-supply = <&refgen>;
+
+ phys = <&mdss1_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss1_dsi0_in: endpoint {
+ remote-endpoint = <&mdss1_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss1_dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss1_dsi0_phy: phy@22094400 {
+ compatible = "qcom,sc8280xp-dsi-phy-5nm",
+ "qcom,sa8775p-dsi-phy-5nm";
+ reg = <0 0x22094400 0 0x200>,
+ <0 0x22094600 0 0x280>,
+ <0 0x22094900 0 0x280>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
+ mdss1_dsi1: dsi@22096000 {
+ compatible = "qcom,sc8280xp-dsi-ctrl",
+ "qcom,sa8775p-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0 0x22096000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss1>;
+ interrupts = <5>;
+
+ clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK>,
+ <&dispcc1 DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&dispcc1 DISP_CC_MDSS_PCLK1_CLK>,
+ <&dispcc1 DISP_CC_MDSS_ESC1_CLK>,
+ <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK_SRC>,
+ <&dispcc1 DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ refgen-supply = <&refgen>;
+
+ phys = <&mdss1_dsi1_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss1_dsi1_in: endpoint {
+ remote-endpoint = <&mdss1_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss1_dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss1_dsi1_phy: phy@22096400 {
+ compatible = "qcom,sc8280xp-dsi-phy-5nm",
+ "qcom,sa8775p-dsi-phy-5nm";
+ reg = <0 0x22096400 0 0x200>,
+ <0 0x22096600 0 0x280>,
+ <0 0x22096900 0 0x280>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
mdss1_dp1: displayport-controller@22098000 {
compatible = "qcom,sc8280xp-dp";
reg = <0 0x22098000 0 0x200>,
<&mdss1_dp2_phy 1>,
<&mdss1_dp3_phy 0>,
<&mdss1_dp3_phy 1>,
- <0>,
- <0>,
- <0>,
- <0>;
+ <&mdss1_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>,
+ <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>;
power-domains = <&rpmhpd SC8280XP_MMCX>;
#clock-cells = <1>;
projects / thirdparty / kernel / stable.git / commitdiff
