]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: renesas: r8a779g0: Restore sort order
authorGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 20 Jan 2025 11:09:12 +0000 (12:09 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 21 Feb 2025 15:23:00 +0000 (16:23 +0100)
Numerical by unit address, but grouped by type.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/ccd215c1146b84c085908e01966f7036be51afa8.1737370801.git.geert+renesas@glider.be
arch/arm64/boot/dts/renesas/r8a779g0.dtsi

index 104f740d20d315d43af9d0e63e418155f14a600c..550e7dabd1da1b23ab601371dbb27d247f152c6d 100644 (file)
                        iommus = <&ipmmu_vi1 7>;
                };
 
+               fcpvx0: fcp@fedb0000 {
+                       compatible = "renesas,fcpv";
+                       reg = <0 0xfedb0000 0 0x200>;
+                       clocks = <&cpg CPG_MOD 1100>;
+                       power-domains = <&sysc R8A779G0_PD_A3ISP0>;
+                       resets = <&cpg 1100>;
+                       iommus = <&ipmmu_vi1 24>;
+               };
+
+               fcpvx1: fcp@fedb8000 {
+                       compatible = "renesas,fcpv";
+                       reg = <0 0xfedb8000 0 0x200>;
+                       clocks = <&cpg CPG_MOD 1101>;
+                       power-domains = <&sysc R8A779G0_PD_A3ISP1>;
+                       resets = <&cpg 1101>;
+                       iommus = <&ipmmu_vi1 25>;
+               };
+
                vspd0: vsp@fea20000 {
                        compatible = "renesas,vsp2";
                        reg = <0 0xfea20000 0 0x7000>;
                        renesas,fcp = <&fcpvd1>;
                };
 
+               vspx0: vsp@fedd0000 {
+                       compatible = "renesas,vsp2";
+                       reg = <0 0xfedd0000 0 0x8000>;
+                       interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 1028>;
+                       power-domains = <&sysc R8A779G0_PD_A3ISP0>;
+                       resets = <&cpg 1028>;
+
+                       renesas,fcp = <&fcpvx0>;
+               };
+
+               vspx1: vsp@fedd8000 {
+                       compatible = "renesas,vsp2";
+                       reg = <0 0xfedd8000 0 0x8000>;
+                       interrupts = <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 1029>;
+                       power-domains = <&sysc R8A779G0_PD_A3ISP1>;
+                       resets = <&cpg 1029>;
+
+                       renesas,fcp = <&fcpvx1>;
+               };
+
                du: display@feb00000 {
                        compatible = "renesas,du-r8a779g0";
                        reg = <0 0xfeb00000 0 0x40000>;
                        };
                };
 
-               fcpvx0: fcp@fedb0000 {
-                       compatible = "renesas,fcpv";
-                       reg = <0 0xfedb0000 0 0x200>;
-                       clocks = <&cpg CPG_MOD 1100>;
-                       power-domains = <&sysc R8A779G0_PD_A3ISP0>;
-                       resets = <&cpg 1100>;
-                       iommus = <&ipmmu_vi1 24>;
-               };
-
-               fcpvx1: fcp@fedb8000 {
-                       compatible = "renesas,fcpv";
-                       reg = <0 0xfedb8000 0 0x200>;
-                       clocks = <&cpg CPG_MOD 1101>;
-                       power-domains = <&sysc R8A779G0_PD_A3ISP1>;
-                       resets = <&cpg 1101>;
-                       iommus = <&ipmmu_vi1 25>;
-               };
-
-               vspx0: vsp@fedd0000 {
-                       compatible = "renesas,vsp2";
-                       reg = <0 0xfedd0000 0 0x8000>;
-                       interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 1028>;
-                       power-domains = <&sysc R8A779G0_PD_A3ISP0>;
-                       resets = <&cpg 1028>;
-
-                       renesas,fcp = <&fcpvx0>;
-               };
-
-               vspx1: vsp@fedd8000 {
-                       compatible = "renesas,vsp2";
-                       reg = <0 0xfedd8000 0 0x8000>;
-                       interrupts = <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 1029>;
-                       power-domains = <&sysc R8A779G0_PD_A3ISP1>;
-                       resets = <&cpg 1029>;
-
-                       renesas,fcp = <&fcpvx1>;
-               };
-
                prr: chipid@fff00044 {
                        compatible = "renesas,prr";
                        reg = <0 0xfff00044 0 4>;