static int loongarch_eiointc_read(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s,
gpa_t addr, unsigned long *val)
{
- int index, ret = 0;
+ int index;
u64 data = 0;
gpa_t offset;
data = s->coremap[index];
break;
default:
- ret = -EINVAL;
break;
}
*val = data;
- return ret;
+ return 0;
}
static int kvm_eiointc_read(struct kvm_vcpu *vcpu,
struct kvm_io_device *dev,
gpa_t addr, int len, void *val)
{
- int ret = -EINVAL;
unsigned long flags, data, offset;
struct loongarch_eiointc *eiointc = vcpu->kvm->arch.eiointc;
if (!eiointc) {
kvm_err("%s: eiointc irqchip not valid!\n", __func__);
- return -EINVAL;
+ return 0;
}
if (addr & (len - 1)) {
kvm_err("%s: eiointc not aligned addr %llx len %d\n", __func__, addr, len);
- return -EINVAL;
+ return 0;
}
offset = addr & 0x7;
addr -= offset;
vcpu->stat.eiointc_read_exits++;
spin_lock_irqsave(&eiointc->lock, flags);
- ret = loongarch_eiointc_read(vcpu, eiointc, addr, &data);
+ loongarch_eiointc_read(vcpu, eiointc, addr, &data);
spin_unlock_irqrestore(&eiointc->lock, flags);
- if (ret)
- return ret;
data = data >> (offset * 8);
switch (len) {
struct loongarch_eiointc *s,
gpa_t addr, u64 value, u64 field_mask)
{
- int index, irq, ret = 0;
+ int index, irq;
u8 cpu;
u64 data, old, mask;
gpa_t offset;
eiointc_update_sw_coremap(s, index * 8, data, sizeof(data), true);
break;
default:
- ret = -EINVAL;
break;
}
- return ret;
+ return 0;
}
static int kvm_eiointc_write(struct kvm_vcpu *vcpu,
struct kvm_io_device *dev,
gpa_t addr, int len, const void *val)
{
- int ret = -EINVAL;
unsigned long flags, value;
struct loongarch_eiointc *eiointc = vcpu->kvm->arch.eiointc;
if (!eiointc) {
kvm_err("%s: eiointc irqchip not valid!\n", __func__);
- return -EINVAL;
+ return 0;
}
if (addr & (len - 1)) {
kvm_err("%s: eiointc not aligned addr %llx len %d\n", __func__, addr, len);
- return -EINVAL;
+ return 0;
}
vcpu->stat.eiointc_write_exits++;
switch (len) {
case 1:
value = *(unsigned char *)val;
- ret = loongarch_eiointc_write(vcpu, eiointc, addr, value, 0xFF);
+ loongarch_eiointc_write(vcpu, eiointc, addr, value, 0xFF);
break;
case 2:
value = *(unsigned short *)val;
- ret = loongarch_eiointc_write(vcpu, eiointc, addr, value, USHRT_MAX);
+ loongarch_eiointc_write(vcpu, eiointc, addr, value, USHRT_MAX);
break;
case 4:
value = *(unsigned int *)val;
- ret = loongarch_eiointc_write(vcpu, eiointc, addr, value, UINT_MAX);
+ loongarch_eiointc_write(vcpu, eiointc, addr, value, UINT_MAX);
break;
default:
value = *(unsigned long *)val;
- ret = loongarch_eiointc_write(vcpu, eiointc, addr, value, ULONG_MAX);
+ loongarch_eiointc_write(vcpu, eiointc, addr, value, ULONG_MAX);
break;
}
spin_unlock_irqrestore(&eiointc->lock, flags);
- return ret;
+ return 0;
}
static const struct kvm_io_device_ops kvm_eiointc_ops = {
if (!eiointc) {
kvm_err("%s: eiointc irqchip not valid!\n", __func__);
- return -EINVAL;
+ return 0;
}
addr -= EIOINTC_VIRT_BASE;
struct kvm_io_device *dev,
gpa_t addr, int len, const void *val)
{
- int ret = 0;
unsigned long flags;
u32 value = *(u32 *)val;
struct loongarch_eiointc *eiointc = vcpu->kvm->arch.eiointc;
if (!eiointc) {
kvm_err("%s: eiointc irqchip not valid!\n", __func__);
- return -EINVAL;
+ return 0;
}
addr -= EIOINTC_VIRT_BASE;
spin_lock_irqsave(&eiointc->lock, flags);
switch (addr) {
case EIOINTC_VIRT_FEATURES:
- ret = -EPERM;
break;
case EIOINTC_VIRT_CONFIG:
/*
* eiointc features can only be set at disabled status
*/
if ((eiointc->status & BIT(EIOINTC_ENABLE)) && value) {
- ret = -EPERM;
break;
}
eiointc->status = value & eiointc->features;
}
spin_unlock_irqrestore(&eiointc->lock, flags);
- return ret;
+ return 0;
}
static const struct kvm_io_device_ops kvm_eiointc_virt_ops = {
vcpu = kvm_get_vcpu_by_cpuid(kvm, cpu);
if (unlikely(vcpu == NULL)) {
kvm_err("%s: invalid target cpu: %d\n", __func__, cpu);
- return -EINVAL;
+ return 0;
}
mailbox = ((data & 0xffffffff) >> 2) & 0x7;
offset = IOCSR_IPI_BUF_20 + mailbox * 4;
srcu_read_unlock(&vcpu->kvm->srcu, idx);
if (unlikely(ret)) {
kvm_err("%s: : read data from addr %llx failed\n", __func__, addr);
- return ret;
+ return 0;
}
/* Construct the mask by scanning the bit 27-30 */
for (i = 0; i < 4; i++) {
if (unlikely(ret))
kvm_err("%s: : write data to addr %llx failed\n", __func__, addr);
- return ret;
+ return 0;
}
static int any_send(struct kvm *kvm, uint64_t data)
vcpu = kvm_get_vcpu_by_cpuid(kvm, cpu);
if (unlikely(vcpu == NULL)) {
kvm_err("%s: invalid target cpu: %d\n", __func__, cpu);
- return -EINVAL;
+ return 0;
}
offset = data & 0xffff;
static int loongarch_ipi_readl(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *val)
{
- int ret = 0;
uint32_t offset;
uint64_t res = 0;
spin_unlock(&vcpu->arch.ipi_state.lock);
break;
case IOCSR_IPI_SET:
- res = 0;
- break;
case IOCSR_IPI_CLEAR:
- res = 0;
break;
case IOCSR_IPI_BUF_20 ... IOCSR_IPI_BUF_38 + 7:
if (offset + len > IOCSR_IPI_BUF_38 + 8) {
kvm_err("%s: invalid offset or len: offset = %d, len = %d\n",
__func__, offset, len);
- ret = -EINVAL;
break;
}
res = read_mailbox(vcpu, offset, len);
break;
default:
kvm_err("%s: unknown addr: %llx\n", __func__, addr);
- ret = -EINVAL;
break;
}
*(uint64_t *)val = res;
- return ret;
+ return 0;
}
static int loongarch_ipi_writel(struct kvm_vcpu *vcpu, gpa_t addr, int len, const void *val)
{
- int ret = 0;
uint64_t data;
uint32_t offset;
switch (offset) {
case IOCSR_IPI_STATUS:
- ret = -EINVAL;
break;
case IOCSR_IPI_EN:
spin_lock(&vcpu->arch.ipi_state.lock);
if (offset + len > IOCSR_IPI_BUF_38 + 8) {
kvm_err("%s: invalid offset or len: offset = %d, len = %d\n",
__func__, offset, len);
- ret = -EINVAL;
break;
}
write_mailbox(vcpu, offset, data, len);
ipi_send(vcpu->kvm, data);
break;
case IOCSR_MAIL_SEND:
- ret = mail_send(vcpu->kvm, data);
+ mail_send(vcpu->kvm, data);
break;
case IOCSR_ANY_SEND:
- ret = any_send(vcpu->kvm, data);
+ any_send(vcpu->kvm, data);
break;
default:
kvm_err("%s: unknown addr: %llx\n", __func__, addr);
- ret = -EINVAL;
break;
}
- return ret;
+ return 0;
}
static int kvm_ipi_read(struct kvm_vcpu *vcpu,
static int loongarch_pch_pic_read(struct loongarch_pch_pic *s, gpa_t addr, int len, void *val)
{
- int ret = 0, offset;
+ int offset;
u64 data = 0;
void *ptemp;
data = s->isr;
break;
default:
- ret = -EINVAL;
+ break;
}
spin_unlock(&s->lock);
- if (ret == 0) {
- offset = (addr - s->pch_pic_base) & 7;
- data = data >> (offset * 8);
- memcpy(val, &data, len);
- }
+ offset = (addr - s->pch_pic_base) & 7;
+ data = data >> (offset * 8);
+ memcpy(val, &data, len);
- return ret;
+ return 0;
}
static int kvm_pch_pic_read(struct kvm_vcpu *vcpu,
struct kvm_io_device *dev,
gpa_t addr, int len, void *val)
{
- int ret;
+ int ret = 0;
struct loongarch_pch_pic *s = vcpu->kvm->arch.pch_pic;
if (!s) {
kvm_err("%s: pch pic irqchip not valid!\n", __func__);
- return -EINVAL;
+ return ret;
}
if (addr & (len - 1)) {
kvm_err("%s: pch pic not aligned addr %llx len %d\n", __func__, addr, len);
- return -EINVAL;
+ return ret;
}
/* statistics of pch pic reading */
static int loongarch_pch_pic_write(struct loongarch_pch_pic *s, gpa_t addr,
int len, const void *val)
{
- int ret = 0, offset;
+ int offset;
u64 old, data, mask;
void *ptemp;
case PCH_PIC_ROUTE_ENTRY_START ... PCH_PIC_ROUTE_ENTRY_END:
break;
default:
- ret = -EINVAL;
break;
}
spin_unlock(&s->lock);
- return ret;
+ return 0;
}
static int kvm_pch_pic_write(struct kvm_vcpu *vcpu,
struct kvm_io_device *dev,
gpa_t addr, int len, const void *val)
{
- int ret;
+ int ret = 0;
struct loongarch_pch_pic *s = vcpu->kvm->arch.pch_pic;
if (!s) {
kvm_err("%s: pch pic irqchip not valid!\n", __func__);
- return -EINVAL;
+ return ret;
}
if (addr & (len - 1)) {
kvm_err("%s: pch pic not aligned addr %llx len %d\n", __func__, addr, len);
- return -EINVAL;
+ return ret;
}
/* statistics of pch pic writing */