]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
RDMA/bnxt_re: Enhance RoCE SRIOV resource configuration design
authorBhargava Chenna Marreddy <bhargava.marreddy@broadcom.com>
Wed, 6 Nov 2024 08:44:35 +0000 (00:44 -0800)
committerLeon Romanovsky <leon@kernel.org>
Tue, 12 Nov 2024 08:04:04 +0000 (03:04 -0500)
Refine RoCE SRIOV resource configuration design,
using the INITIALIZE_FW's flag as an indication
for the new design to the firmware. RoCE driver does not
have to provision resources to VF when firmware
advertises support for RoCE resource management by NIC driver.

Signed-off-by: Bhargava Chenna Marreddy <bhargava.marreddy@broadcom.com>
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Vikas Gupta <vikas.gupta@broadcom.com>
Reviewed-by: Selvin Xavier <selvin.xavier@broadcom.com>
CC: Michael Chan <michael.chan@broadcom.com>
Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com>
Link: https://patch.msgid.link/1730882676-24434-3-git-send-email-selvin.xavier@broadcom.com
Signed-off-by: Leon Romanovsky <leon@kernel.org>
drivers/infiniband/hw/bnxt_re/main.c
drivers/infiniband/hw/bnxt_re/qplib_rcfw.c
drivers/infiniband/hw/bnxt_re/qplib_res.h
drivers/infiniband/hw/bnxt_re/roce_hsi.h
drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c
drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.h

index 4127227a944715c8b753c083cc782840e36d19b9..dd528dd63d537db124c2bb7ff5891e55974071ba 100644 (file)
@@ -184,6 +184,7 @@ static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev)
        rdev->rcfw.res = &rdev->qplib_res;
        rdev->qplib_res.dattr = &rdev->dev_attr;
        rdev->qplib_res.is_vf = BNXT_EN_VF(en_dev);
+       rdev->qplib_res.en_dev = en_dev;
 
        bnxt_re_set_drv_mode(rdev);
 
@@ -285,6 +286,10 @@ static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev)
 
 static void bnxt_re_vf_res_config(struct bnxt_re_dev *rdev)
 {
+       /*
+        * Use the total VF count since the actual VF count may not be
+        * available at this point.
+        */
        rdev->num_vfs = pci_sriov_get_totalvfs(rdev->en_dev->pdev);
        if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) {
                bnxt_re_set_resource_limits(rdev);
@@ -2056,11 +2061,9 @@ static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 op_type)
                INIT_DELAYED_WORK(&rdev->worker, bnxt_re_worker);
                set_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags);
                schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000));
-               /*
-                * Use the total VF count since the actual VF count may not be
-                * available at this point.
-                */
-               bnxt_re_vf_res_config(rdev);
+
+               if (!(rdev->qplib_res.en_dev->flags & BNXT_EN_FLAG_ROCE_VF_RES_MGMT))
+                       bnxt_re_vf_res_config(rdev);
        }
        hash_init(rdev->cq_hash);
        if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT)
index f5713e3c39fb933cac6b93d47633a728b2f60a51..005079b037f45443dc285094d2385bad736aeba8 100644 (file)
@@ -910,6 +910,8 @@ skip_ctx_setup:
                flags |= CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED;
        if (_is_optimize_modify_qp_supported(rcfw->res->dattr->dev_cap_flags2))
                flags |= CMDQ_INITIALIZE_FW_FLAGS_OPTIMIZE_MODIFY_QP_SUPPORTED;
+       if (rcfw->res->en_dev->flags & BNXT_EN_FLAG_ROCE_VF_RES_MGMT)
+               flags |= CMDQ_INITIALIZE_FW_FLAGS_L2_VF_RESOURCE_MGMT;
        req.flags |= cpu_to_le16(flags);
        req.stat_ctx_id = cpu_to_le32(ctx->stats.fw_id);
        bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0);
index 115910c7e56dcf8927463f5128721930f0e86a26..21fb148713a6f918449b49a47e9140329fc7c5f1 100644 (file)
@@ -39,6 +39,8 @@
 #ifndef __BNXT_QPLIB_RES_H__
 #define __BNXT_QPLIB_RES_H__
 
+#include "bnxt_ulp.h"
+
 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;
 
 #define CHIP_NUM_57508         0x1750
@@ -302,6 +304,7 @@ struct bnxt_qplib_res {
        struct bnxt_qplib_chip_ctx      *cctx;
        struct bnxt_qplib_dev_attr      *dattr;
        struct net_device               *netdev;
+       struct bnxt_en_dev              *en_dev;
        struct bnxt_qplib_rcfw          *rcfw;
        struct bnxt_qplib_pd_tbl        pd_tbl;
        /* To protect the pd table bit map */
index d9c53731871ea711a2ee72123ab858e575e80eb9..a98fc9c2313e7e0cb8b38dc09afcfeaa8c3a51e6 100644 (file)
@@ -217,6 +217,7 @@ struct cmdq_initialize_fw {
        #define CMDQ_INITIALIZE_FW_FLAGS_MRAV_RESERVATION_SPLIT          0x1UL
        #define CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED     0x2UL
        #define CMDQ_INITIALIZE_FW_FLAGS_OPTIMIZE_MODIFY_QP_SUPPORTED    0x8UL
+       #define CMDQ_INITIALIZE_FW_FLAGS_L2_VF_RESOURCE_MGMT             0x10UL
        __le16  cookie;
        u8      resp_size;
        u8      reserved8;
index fdd6356f21efb3c0c2e62c88f4895cc1a523c945..b771c84cdd8951482021fcadf10e01f9519c774a 100644 (file)
@@ -414,6 +414,8 @@ static void bnxt_set_edev_info(struct bnxt_en_dev *edev, struct bnxt *bp)
                edev->flags |= BNXT_EN_FLAG_ROCEV2_CAP;
        if (bp->flags & BNXT_FLAG_VF)
                edev->flags |= BNXT_EN_FLAG_VF;
+       if (BNXT_ROCE_VF_RESC_CAP(bp))
+               edev->flags |= BNXT_EN_FLAG_ROCE_VF_RES_MGMT;
 
        edev->chip_num = bp->chip_num;
        edev->hw_ring_stats_size = bp->hw_ring_stats_size;
index 4f4914f5c84c912b5c579b5f2f71a89da617bc3b..5d6aac60f2365038d3e2f7f59d3a6bed7d2fc1a5 100644 (file)
@@ -64,6 +64,7 @@ struct bnxt_en_dev {
        #define BNXT_EN_FLAG_ULP_STOPPED        0x8
        #define BNXT_EN_FLAG_VF                 0x10
 #define BNXT_EN_VF(edev)       ((edev)->flags & BNXT_EN_FLAG_VF)
+       #define BNXT_EN_FLAG_ROCE_VF_RES_MGMT   0x20
 
        struct bnxt_ulp                 *ulp_tbl;
        int                             l2_db_size;     /* Doorbell BAR size in