re PR target/91533 (abs pattern generates MMX instructions but fails to call EMMS)

	PR target/91533
	Backport from mainline
	2019-06-30  Uroš Bizjak  <ubizjak@gmail.com>

	* config/i386/sse.md (ssse3_abs<mode>2): Rename from abs<mode>2.
	* config/i386/i386-builtin.def (__builtin_ia32_pabsb):
	Use CODE_FOR_ssse3_absv8qi2.
	(__builtin_ia32_pabsw): Use CODE_FOR_ssse3_absv4hi2.
	(__builtin_ia32_pabsd): Use CODE_FOR_ssse3_absv2si2.

From-SVN: r274910

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 44d83990d6d9619dc73ec9a0a153c0d77fec4358..9ed32f2ddc3d5721354fdda15b6e5ed63c2ee40f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2019-08-25  Uroš Bizjak  <ubizjak@gmail.com>
+
+       PR target/91533
+       Backport from mainline
+       2019-06-30  Uroš Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/sse.md (ssse3_abs<mode>2): Rename from abs<mode>2.
+       * config/i386/i386-builtin.def (__builtin_ia32_pabsb):
+       Use CODE_FOR_ssse3_absv8qi2.
+       (__builtin_ia32_pabsw): Use CODE_FOR_ssse3_absv4hi2.
+       (__builtin_ia32_pabsd): Use CODE_FOR_ssse3_absv2si2.
+
 2019-08-23  Mihailo Stojanovic  <mistojanovic@wavecomp.com>
 
        Backport from mainline
@@ -683,7 +695,7 @@
 
 2019-07-11  Uroš Bizjak  <ubizjak@gmail.com>
 
-       Backported from mainline
+       Backport from mainline
        2019-07-06  Richard Sandiford  <richard.sandiford@arm.com>
 
        * config/i386/sse.md (*andnot<mode>3_bcst): Fix VI/VI48_AVX512VL typo.

diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 6580890edc08468d60ac633208f17b100b94c1d0..5dedeb2d18b6a136ce752068088ddd54f3f266f4 100644 (file)
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -818,11 +818,11 @@ BDESC (OPTION_MASK_ISA_SSE3, 0, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd"
 
 /* SSSE3 */
 BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI)
-BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI)
+BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI)
 BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI)
-BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI)
+BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI)
 BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI)
-BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI)
+BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI)
 
 BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI)
 BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 46ec4602eb7bdff2465e8cf203a7bb8379449925..152b7cc77f189087e056aacbcd9696b5f111e332 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -16241,7 +16241,7 @@
     }
 })
 
-(define_insn "abs<mode>2"
+(define_insn "ssse3_abs<mode>2"
   [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
        (abs:MMXMODEI
          (match_operand:MMXMODEI 1 "nonimmediate_operand" "ym")))]