powerpc: Set missing wakeup bit in LPCR on POWER9

commit 7a43906f5cbfb74712af168988455e350707e310 upstream.

There is a new bit, LPCR_PECE_HVEE (Hypervisor Virtualization Exit
Enable), which controls wakeup from STOP states on Hypervisor
Virtualization Interrupts (which happen to also be all external
interrupts in host or bare metal mode).

It needs to be set or we will miss wakeups.

Fixes: 9baaef0a22c8 ("powerpc/irq: Add support for HV virtualization interrupts")
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[mpe: Rename it to HVEE to match the name in the ISA]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 978dada662aec866ad84355982d0788f1251d96b..52cbf043e9602b8c7e67489a7943e9dd63b0a50e 100644 (file)
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -355,6 +355,7 @@
 #define     LPCR_PECE0         ASM_CONST(0x0000000000004000)   /* ext. exceptions can cause exit */
 #define     LPCR_PECE1         ASM_CONST(0x0000000000002000)   /* decrementer can cause exit */
 #define     LPCR_PECE2         ASM_CONST(0x0000000000001000)   /* machine check etc can cause exit */
+#define     LPCR_PECE_HVEE     ASM_CONST(0x0000400000000000)   /* P9 Wakeup on HV interrupts */
 #define   LPCR_MER             ASM_CONST(0x0000000000000800)   /* Mediated External Exception */
 #define   LPCR_MER_SH          11
 #define   LPCR_TC              ASM_CONST(0x0000000000000200)   /* Translation control */

diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index 52ff3f025437947484d7567141b5d3802cc887c2..37c027ca83b2b172a07a9ed01b23ec3e34baffff 100644 (file)
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -98,8 +98,8 @@ _GLOBAL(__setup_cpu_power9)
        li      r0,0
        mtspr   SPRN_LPID,r0
        mfspr   r3,SPRN_LPCR
-       ori     r3, r3, LPCR_PECEDH
-       ori     r3, r3, LPCR_HVICE
+       LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE)
+       or      r3, r3, r4
        bl      __init_LPCR
        bl      __init_HFSCR
        bl      __init_tlb_power9
@@ -118,8 +118,8 @@ _GLOBAL(__restore_cpu_power9)
        li      r0,0
        mtspr   SPRN_LPID,r0
        mfspr   r3,SPRN_LPCR
-       ori     r3, r3, LPCR_PECEDH
-       ori     r3, r3, LPCR_HVICE
+       LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE)
+       or      r3, r3, r4
        bl      __init_LPCR
        bl      __init_HFSCR
        bl      __init_tlb_power9