]> git.ipfire.org Git - thirdparty/libvirt.git/commitdiff
cpu: Add SandyBridge-IBRS CPU model
authorJiri Denemark <jdenemar@redhat.com>
Mon, 8 Jan 2018 19:53:25 +0000 (20:53 +0100)
committerJiri Denemark <jdenemar@redhat.com>
Wed, 17 Jan 2018 16:07:03 +0000 (17:07 +0100)
This is a variant of SandyBridge with indirect branch prediction
protection. The only difference between SandyBridge and SandyBridge-IBRS
is the added "spec-ctrl" feature.

The SandyBridge-IBRS model in QEMU is a bit different since SandyBridge
got several additional features since we added it in cpu_map.xml:
    arat, vme, xsaveopt

Adding them only to the -IBRS variant would confuse our CPU detection
code.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Pavel Hrdina <phrdina@redhat.com>
src/cpu/cpu_map.xml

index 1536b4f9f1ea25131f516479a7dab1dc510d99a2..af23ed43e8cc4204d7992f7767f49faf6fea3d28 100644 (file)
       <feature name='xsave'/>
     </model>
 
+    <model name='SandyBridge-IBRS'>
+      <signature family='6' model='42'/>
+      <vendor name='Intel'/>
+      <feature name='aes'/>
+      <feature name='apic'/>
+      <feature name='avx'/>
+      <feature name='clflush'/>
+      <feature name='cmov'/>
+      <feature name='cx16'/>
+      <feature name='cx8'/>
+      <feature name='de'/>
+      <feature name='fpu'/>
+      <feature name='fxsr'/>
+      <feature name='lahf_lm'/>
+      <feature name='lm'/>
+      <feature name='mca'/>
+      <feature name='mce'/>
+      <feature name='mmx'/>
+      <feature name='msr'/>
+      <feature name='mtrr'/>
+      <feature name='nx'/>
+      <feature name='pae'/>
+      <feature name='pat'/>
+      <feature name='pclmuldq'/>
+      <feature name='pge'/>
+      <feature name='pni'/>
+      <feature name='popcnt'/>
+      <feature name='pse'/>
+      <feature name='pse36'/>
+      <feature name='rdtscp'/>
+      <feature name='sep'/>
+      <feature name='spec-ctrl'/>
+      <feature name='sse'/>
+      <feature name='sse2'/>
+      <feature name='sse4.1'/>
+      <feature name='sse4.2'/>
+      <feature name='ssse3'/>
+      <feature name='syscall'/>
+      <feature name='tsc'/>
+      <feature name='tsc-deadline'/>
+      <feature name='x2apic'/>
+      <feature name='xsave'/>
+    </model>
+
     <model name='IvyBridge'>
       <signature family='6' model='58'/>
       <vendor name='Intel'/>