)
);
+TRACE_EVENT(amd_pstate_cppc_req2,
+
+ TP_PROTO(unsigned int cpu_id,
+ u8 floor_perf,
+ bool changed,
+ int err_code
+ ),
+
+ TP_ARGS(cpu_id,
+ floor_perf,
+ changed,
+ err_code),
+
+ TP_STRUCT__entry(
+ __field(unsigned int, cpu_id)
+ __field(u8, floor_perf)
+ __field(bool, changed)
+ __field(int, err_code)
+ ),
+
+ TP_fast_assign(
+ __entry->cpu_id = cpu_id;
+ __entry->floor_perf = floor_perf;
+ __entry->changed = changed;
+ __entry->err_code = err_code;
+ ),
+
+ TP_printk("cpu%u: floor_perf=%u, changed=%u (error = %d)",
+ __entry->cpu_id,
+ __entry->floor_perf,
+ __entry->changed,
+ __entry->err_code
+ )
+);
+
#endif /* _AMD_PSTATE_TRACE_H */
/* This part must be outside protection */
{
struct amd_cpudata *cpudata = policy->driver_data;
u64 value, prev;
+ bool changed;
int ret;
if (!cpu_feature_enabled(X86_FEATURE_CPPC_PERF_PRIO))
value = prev = READ_ONCE(cpudata->cppc_req2_cached);
FIELD_MODIFY(AMD_CPPC_FLOOR_PERF_MASK, &value, perf);
- if (value == prev)
- return 0;
+ changed = value != prev;
+ if (!changed) {
+ ret = 0;
+ goto out_trace;
+ }
ret = wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ2, value);
if (ret) {
+ changed = false;
pr_err("failed to set CPPC REQ2 value. Error (%d)\n", ret);
- return ret;
+ goto out_trace;
}
WRITE_ONCE(cpudata->cppc_req2_cached, value);
+out_trace:
+ if (trace_amd_pstate_cppc_req2_enabled())
+ trace_amd_pstate_cppc_req2(cpudata->cpu, perf, changed, ret);
return ret;
}