{
struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
int barno = (unsigned long)attr->private;
- struct resource *res = pci_resource_n(pdev, barno);
enum pci_mmap_state mmap_type;
struct pci_bus_region bar;
int ret;
if (ret)
return ret;
- if (res->flags & IORESOURCE_MEM && iomem_is_exclusive(res->start))
+ if (pci_resource_is_mem(pdev, barno) &&
+ iomem_is_exclusive(pci_resource_start(pdev, barno)))
return -EINVAL;
if (!__pci_mmap_fits(pdev, barno, vma, sparse))
return -EINVAL;
- pcibios_resource_to_bus(pdev->bus, &bar, res);
+ pcibios_resource_to_bus(pdev->bus, &bar, pci_resource_n(pdev, barno));
vma->vm_pgoff += bar.start >> (PAGE_SHIFT - (sparse ? 5 : 0));
- mmap_type = res->flags & IORESOURCE_MEM ? pci_mmap_mem : pci_mmap_io;
+ mmap_type = pci_resource_is_mem(pdev, barno) ? pci_mmap_mem : pci_mmap_io;
return hose_mmap_page_range(pdev->sysdata, vma, mmap_type, sparse);
}
long dense_offset;
unsigned long sparse_size;
- pcibios_resource_to_bus(pdev->bus, &bar, &pdev->resource[num]);
+ pcibios_resource_to_bus(pdev->bus, &bar, pci_resource_n(pdev, num));
/* All core logic chips have 4G sparse address space, except
CIA which has 16G (see xxx_SPARSE_MEM and xxx_DENSE_MEM
suffix = ""; /* Assume bwx machine, normal resourceN files. */
nlen1 = 10;
- if (pdev->resource[num].flags & IORESOURCE_MEM) {
+ if (pci_resource_is_mem(pdev, num)) {
sparse_base = hose->sparse_mem_base;
dense_base = hose->dense_mem_base;
if (sparse_base && !sparse_mem_mmap_fits(pdev, num)) {