perf/x86/intel: Update event constraints and cache_extra_regsfor SPR

Update perf hard-coded event constraints and cache_extra_regs[] for
Sapphire rapids according to the latest SPR perfmon events (v1.39).

Emerald Rapids (EMR) and Granite Rapids (GNR) share exactly same event
constraints and extra MSR values with SPR. No extra changes are needed
for EMR and GNR.

Please note the change could temporarily impact other platforms which
share the hard coded data structures, but it would be fixed in
subsequent patches soon.

SPR perfmon events:
https://github.com/intel/perfmon/blob/main/SPR/events/sapphirerapids_core.json

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260515061143.338553-3-dapeng1.mi@linux.intel.com

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index db409caef83d13ec663416f60e2e9ab75690c7f5..932f612a99f3f7db0a483b19f6bb51e02cd15e89 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -356,11 +356,12 @@ static struct extra_reg intel_glc_extra_regs[] __read_mostly = {
 
 static struct event_constraint intel_glc_event_constraints[] = {
        FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
-       FIXED_EVENT_CONSTRAINT(0x0100, 0),      /* INST_RETIRED.PREC_DIST */
+       FIXED_EVENT_CONSTRAINT(0x0100, 0),      /* pseudo INST_RETIRED.ANY */
        FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
-       FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
+       FIXED_EVENT_CONSTRAINT(0x0200, 1),      /* pseudo CPU_CLK_UNHALTED.THREAD */
+       FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* pseudo CPU_CLK_UNHALTED.REF_TSC */
        FIXED_EVENT_CONSTRAINT(0x013c, 2),      /* CPU_CLK_UNHALTED.REF_TSC_P */
-       FIXED_EVENT_CONSTRAINT(0x0400, 3),      /* SLOTS */
+       FIXED_EVENT_CONSTRAINT(0x0400, 3),      /* pseudo TOPDOWN.SLOTS */
        METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
        METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
        METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
@@ -380,9 +381,13 @@ static struct event_constraint intel_glc_event_constraints[] = {
 
        INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
        INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
+       INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf),
+       INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf),
        INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
+       INTEL_UEVENT_CONSTRAINT(0x0ca3, 0xf),
        INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
        INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
+       INTEL_UEVENT_CONSTRAINT(0x01cd, 0xfe),
        INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
        INTEL_EVENT_CONSTRAINT(0xce, 0x1),
        INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
@@ -714,18 +719,18 @@ static __initconst const u64 glc_hw_cache_extra_regs
 {
  [ C(LL  ) ] = {
        [ C(OP_READ) ] = {
-               [ C(RESULT_ACCESS) ] = 0x10001,
-               [ C(RESULT_MISS)   ] = 0x3fbfc00001,
+               [ C(RESULT_ACCESS) ] = 0x10001,         /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
+               [ C(RESULT_MISS)   ] = 0x3fbfc00001,    /* OCR.DEMAND_DATA_RD.L3_MISS */
        },
        [ C(OP_WRITE) ] = {
-               [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
-               [ C(RESULT_MISS)   ] = 0x3f3fc00002,
+               [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,    /* OCR.DEMAND_RFO.ANY_RESPONSE */
+               [ C(RESULT_MISS)   ] = 0x3f3fc00002,    /* OCR.DEMAND_RFO.L3_MISS */
        },
  },
  [ C(NODE) ] = {
        [ C(OP_READ) ] = {
-               [ C(RESULT_ACCESS) ] = 0x10c000001,
-               [ C(RESULT_MISS)   ] = 0x3fb3000001,
+               [ C(RESULT_ACCESS) ] = 0x104000001,     /* OCR.DEMAND_DATA_RD.LOCAL_DRAM */
+               [ C(RESULT_MISS)   ] = 0x730000001,     /* OCR.DEMAND_DATA_RD.REMOTE_DRAM */
        },
  },
 };