]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: mb-smarc-2: Add PCIe support
authorAlexander Stein <alexander.stein@ew.tq-group.com>
Wed, 17 Dec 2025 08:48:04 +0000 (09:48 +0100)
committerShawn Guo <shawnguo@kernel.org>
Tue, 30 Dec 2025 08:30:21 +0000 (16:30 +0800)
TQMa8XxS on MB-SMARC-2 supports mPCIe on X44.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi
arch/arm64/boot/dts/freescale/tqma8xxs.dtsi

index 8bfe77113d64b943f6c7c76f7cf2f1e4615b88be..050ae23c4dc1e4528eacb320ff8853f3daa55904 100644 (file)
        status = "okay";
 };
 
+&hsio_phy {
+       fsl,hsio-cfg = "pciea-x2-pcieb";
+       fsl,refclk-pad-mode = "input";
+       status = "okay";
+};
+
 &i2c0 {
        tlv320aic3x04: audio-codec@18 {
                compatible = "ti,tlv320aic32x4";
        status = "okay";
 };
 
+&pcieb {
+       status = "okay";
+};
+
 &reg_sdvmmc {
        off-on-delay-us = <200000>;
        status = "okay";
index ebf20d5b5df9cb27d13cfc7b45c13fc683cc608e..bfc918f18d0114a339739ffc492f617756f0be2d 100644 (file)
        status = "okay";
 };
 
+&pcieb {
+       phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
+       phy-names = "pcie-phy";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcieb>;
+       reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
+};
+
 &sai1 {
        assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
                          <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
        };
 
        pinctrl_pcieb: pcieagrp {
-               fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00  0x06000041>,
-                          <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000041>,
-                          <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02   0x04000041>;
+               fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00          0x06000041>,
+                          <IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B     0x06000041>,
+                          <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02           0x04000041>;
        };
 
        pinctrl_pwm_mipi_lvds0: mipi-lvds0-pwmgrp {