RISC-V: Add vmsbc C++ API tests

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/base/vmsbc_vv-1.C: New test.
	* g++.target/riscv/rvv/base/vmsbc_vv-2.C: New test.
	* g++.target/riscv/rvv/base/vmsbc_vv-3.C: New test.
	* g++.target/riscv/rvv/base/vmsbc_vvm-1.C: New test.
	* g++.target/riscv/rvv/base/vmsbc_vvm-2.C: New test.
	* g++.target/riscv/rvv/base/vmsbc_vvm-3.C: New test.
	* g++.target/riscv/rvv/base/vmsbc_vx_rv32-1.C: New test.
	* g++.target/riscv/rvv/base/vmsbc_vx_rv32-2.C: New test.
	* g++.target/riscv/rvv/base/vmsbc_vx_rv32-3.C: New test.
	* g++.target/riscv/rvv/base/vmsbc_vx_rv64-1.C: New test.
	* g++.target/riscv/rvv/base/vmsbc_vx_rv64-2.C: New test.
	* g++.target/riscv/rvv/base/vmsbc_vx_rv64-3.C: New test.
	* g++.target/riscv/rvv/base/vmsbc_vxm_rv32-1.C: New test.
	* g++.target/riscv/rvv/base/vmsbc_vxm_rv32-2.C: New test.
	* g++.target/riscv/rvv/base/vmsbc_vxm_rv32-3.C: New test.
	* g++.target/riscv/rvv/base/vmsbc_vxm_rv64-1.C: New test.
	* g++.target/riscv/rvv/base/vmsbc_vxm_rv64-2.C: New test.
	* g++.target/riscv/rvv/base/vmsbc_vxm_rv64-3.C: New test.

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-1.C
new file mode 100644 (file)
index 0000000..b90a518
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-2.C
new file mode 100644 (file)
index 0000000..6c7d272
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-3.C
new file mode 100644 (file)
index 0000000..a2e931c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-1.C
new file mode 100644 (file)
index 0000000..f49cc37
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,vint8mf8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,vint8mf4_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,vint8mf2_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,vint8m1_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,vint8m2_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,vint8m4_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,vint8m8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,vint16mf4_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,vint16mf2_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,vint16m1_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,vint16m2_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,vint16m4_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,vint16m8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,vint32mf2_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,vint32m1_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,vint32m2_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,vint32m4_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,vint32m8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,vint64m1_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,vint64m2_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,vint64m4_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,vint64m8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,vuint8m1_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,vuint8m2_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,vuint8m4_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,vuint8m8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,vuint16m1_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,vuint16m2_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,vuint16m4_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,vuint16m8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,vuint32m1_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,vuint32m2_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,vuint32m4_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,vuint32m8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,vuint64m1_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,vuint64m2_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,vuint64m4_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,vuint64m8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-2.C
new file mode 100644 (file)
index 0000000..c8e23b9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,vint8mf8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,vint8mf4_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,vint8mf2_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,vint8m1_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,vint8m2_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,vint8m4_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,vint8m8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,vint16mf4_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,vint16mf2_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,vint16m1_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,vint16m2_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,vint16m4_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,vint16m8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,vint32mf2_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,vint32m1_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,vint32m2_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,vint32m4_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,vint32m8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,vint64m1_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,vint64m2_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,vint64m4_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,vint64m8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,vuint8m1_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,vuint8m2_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,vuint8m4_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,vuint8m8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,vuint16m1_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,vuint16m2_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,vuint16m4_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,vuint16m8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,vuint32m1_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,vuint32m2_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,vuint32m4_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,vuint32m8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,vuint64m1_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,vuint64m2_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,vuint64m4_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,vuint64m8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-3.C
new file mode 100644 (file)
index 0000000..175c72b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,vint8mf8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,vint8mf4_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,vint8mf2_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,vint8m1_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,vint8m2_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,vint8m4_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,vint8m8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,vint16mf4_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,vint16mf2_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,vint16m1_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,vint16m2_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,vint16m4_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,vint16m8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,vint32mf2_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,vint32m1_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,vint32m2_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,vint32m4_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,vint32m8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,vint64m1_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,vint64m2_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,vint64m4_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,vint64m8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,vuint8m1_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,vuint8m2_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,vuint8m4_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,vuint8m8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,vuint16m1_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,vuint16m2_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,vuint16m4_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,vuint16m8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,vuint32m1_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,vuint32m2_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,vuint32m4_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,vuint32m8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,vuint64m1_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,vuint64m2_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,vuint64m4_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,vuint64m8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-1.C
new file mode 100644 (file)
index 0000000..5de53e3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-1.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-2.C
new file mode 100644 (file)
index 0000000..9eb3ca6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-2.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-3.C
new file mode 100644 (file)
index 0000000..19cd0b9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-3.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vmsbc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-1.C
new file mode 100644 (file)
index 0000000..34db39e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-2.C
new file mode 100644 (file)
index 0000000..3e8189b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-3.C
new file mode 100644 (file)
index 0000000..f4d252b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-1.C
new file mode 100644 (file)
index 0000000..9b8e942
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-1.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-2.C
new file mode 100644 (file)
index 0000000..6d560fc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-2.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-3.C
new file mode 100644 (file)
index 0000000..363d342
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-3.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vmsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-1.C
new file mode 100644 (file)
index 0000000..a37f49d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-2.C
new file mode 100644 (file)
index 0000000..cd47571
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-3.C
new file mode 100644 (file)
index 0000000..892df21
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsbc(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool1_t test___riscv_vmsbc(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool1_t test___riscv_vmsbc(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool2_t test___riscv_vmsbc(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool4_t test___riscv_vmsbc(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool64_t test___riscv_vmsbc(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool32_t test___riscv_vmsbc(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool16_t test___riscv_vmsbc(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+vbool8_t test___riscv_vmsbc(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl)
+{
+    return __riscv_vmsbc(op1,op2,borrowin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */