drm/msm: add PERFCTR_CNTL to ifpc_reglist

commit 6c6915bfea212d32844b2b7f22bc1aa3669eabc4 upstream.

Previously this register would become 0 after IFPC took place which
broke all usages of counters.

Fixes: a6a0157cc68e ("drm/msm/a6xx: Enable IFPC on Adreno X1-85")
Cc: stable@vger.kernel.org
Signed-off-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/690960/
Message-ID: <20251127-ifpc_counters-v3-1-fac0a126bc88@gmail.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 44df6410bce17613702d7d04906469de4dd021b5..2adbc198ecf26d337aef6de9330a1a60d95cda44 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1360,6 +1360,7 @@ static const u32 a750_ifpc_reglist_regs[] = {
        REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),
        REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),
        REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),
+       REG_A6XX_RBBM_PERFCTR_CNTL,
        REG_A6XX_TPL1_NC_MODE_CNTL,
        REG_A6XX_SP_NC_MODE_CNTL,
        REG_A6XX_CP_DBG_ECO_CNTL,