int mt76_connac_init_tx_queues(struct mt76_phy *phy, int idx, int n_desc,
int ring_base, void *wed, u32 flags);
void mt76_connac_set_txpower_cur(struct mt76_phy *phy, s8 max_power);
+s8 mt76_connac_get_rate_power_limit(struct mt76_phy *phy,
+ struct ieee80211_channel *chan,
+ struct mt76_power_limits *limits);
void mt76_connac_write_hw_txp(struct mt76_dev *dev,
struct mt76_tx_info *tx_info,
void *txp_ptr, u32 id);
.hw_value = ch_list[idx],
.band = band,
};
- s8 reg_power, sar_power, max_power;
-
- reg_power = mt76_connac_get_ch_power(phy, &chan,
- tx_power);
- sar_power = mt76_get_sar_power(phy, &chan, reg_power);
-
- max_power = mt76_get_rate_power_limits(phy, &chan, limits,
- sar_power);
+ s8 max_power;
+ max_power = mt76_connac_get_rate_power_limit(phy, &chan,
+ limits);
if (phy->chandef.chan &&
phy->chandef.chan->hw_value == ch_list[idx] &&
phy->chandef.chan->band == band)
}
EXPORT_SYMBOL_GPL(mt76_connac_mcu_rdd_cmd);
+s8 mt76_connac_get_rate_power_limit(struct mt76_phy *phy,
+ struct ieee80211_channel *chan,
+ struct mt76_power_limits *limits)
+{
+ s8 reg_power, sar_power;
+ int tx_power;
+
+ tx_power = 2 * phy->hw->conf.power_level;
+ if (!tx_power)
+ tx_power = 127;
+
+ reg_power = mt76_connac_get_ch_power(phy, chan, tx_power);
+ sar_power = mt76_get_sar_power(phy, chan, reg_power);
+ return mt76_get_rate_power_limits(phy, chan, limits, sar_power);
+}
+EXPORT_SYMBOL_GPL(mt76_connac_get_rate_power_limit);
+
static int
mt76_connac_mcu_send_ram_firmware(struct mt76_dev *dev,
const struct mt76_connac2_fw_trailer *hdr,