[rtlanal.c] Convert conditional compilation on WORD_REGISTER_OPERATIONS

	* rtlanal.c (nonzero_bits1): Convert preprocessor check
	for WORD_REGISTER_OPERATIONS to runtime check.

From-SVN: r235512

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cbfae1ffe66d7f345b5043f39a4dd7afc4b83812..c97041a3afd1d08d62a5c1056344be4b4a04e2cf 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2016-04-27  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * rtlanal.c (nonzero_bits1): Convert preprocessor check
+       for WORD_REGISTER_OPERATIONS to runtime check.
+
 2016-04-27  Richard Biener  <rguenther@suse.de>
 
        PR ipa/70760

diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index b4dff86c0e9a7abff946f834ad8aa76ffcb2aeb9..0b6e1e0e38d18f76a92ddbd43c45f938b0144fe8 100644 (file)
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -4584,13 +4584,14 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
          nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode,
                                          known_x, known_mode, known_ret);
 
-#if WORD_REGISTER_OPERATIONS && defined (LOAD_EXTEND_OP)
+#ifdef LOAD_EXTEND_OP
          /* If this is a typical RISC machine, we only have to worry
             about the way loads are extended.  */
-         if ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
-              ? val_signbit_known_set_p (inner_mode, nonzero)
-              : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND)
-             || !MEM_P (SUBREG_REG (x)))
+         if (WORD_REGISTER_OPERATIONS
+             && ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
+                    ? val_signbit_known_set_p (inner_mode, nonzero)
+                    : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND)
+                  || !MEM_P (SUBREG_REG (x))))
 #endif
            {
              /* On many CISC machines, accessing an object in a wider mode