ARM: dts: microchip: sama5d3: Update the cache configuration for CPU

Add the memory size properties for L1 according with block
diagram from datasheet:

- L1 cache configuration with 32 KB for both data and instruction cache.

[root@sama5d3 ~]$ lscpu
Architecture:             armv7l
  Byte Order:             Little Endian
CPU(s):                   1
  On-line CPU(s) list:    0
Vendor ID:                ARM
  Model name:             Cortex-A5
Caches (sum of all):
  L1d:                    32 KiB (1 instance)
  L1i:                    32 KiB (1 instance)

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20250625064934.4828-3-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

diff --git a/arch/arm/boot/dts/microchip/sama5d3.dtsi b/arch/arm/boot/dts/microchip/sama5d3.dtsi
index e95799c17fdb0a509ee7470f5c3ee690b7c92909..00ba59ac1968c45a5e2cf1f1d9e44b56972e16e8 100644 (file)
--- a/arch/arm/boot/dts/microchip/sama5d3.dtsi
+++ b/arch/arm/boot/dts/microchip/sama5d3.dtsi
@@ -48,6 +48,8 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a5";
                        reg = <0x0>;
+                       d-cache-size = <0x8000>;        // L1, 32 KB
+                       i-cache-size = <0x8000>;        // L1, 32 KB
                };
        };