]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
Add bext pattern for ZBS
authorRaphael Moreira Zinsly <rzinsly@ventanamicro.com>
Sat, 20 May 2023 03:41:12 +0000 (21:41 -0600)
committerJeff Law <jlaw@ventanamicro.com>
Sat, 20 May 2023 03:41:12 +0000 (21:41 -0600)
Changes since v1:
        - Removed name clash change.
        - Fix new pattern indentation.

-- >8 --

When (a & (1 << bit_no)) is tested inside an IF we can use a bit extract.

gcc/ChangeLog:

* config/riscv/bitmanip.md (branch<X:mode>_bext): New split pattern.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbs-bext-02.c: New test.

gcc/config/riscv/bitmanip.md
gcc/testsuite/gcc.target/riscv/zbs-bext-02.c [new file with mode: 0644]

index c2a29e181747c13bbe669c1c60b9ee96cda9dd7c..96d31d92670b27d495dc5a9fbfc07e8767f40976 100644 (file)
    operands[9] = GEN_INT (clearbit);
 })
 
+;; IF_THEN_ELSE: test for (a & (1 << BIT_NO))
+(define_insn_and_split "*branch<X:mode>_bext"
+  [(set (pc)
+       (if_then_else
+         (match_operator 1 "equality_operator"
+         [(zero_extract:X (match_operand:X 2 "register_operand" "r")
+                          (const_int 1)
+                          (zero_extend:X
+                            (match_operand:QI 3 "register_operand" "r")))
+           (const_int 0)])
+       (label_ref (match_operand 0 "" ""))
+       (pc)))
+  (clobber (match_scratch:X 4 "=&r"))]
+  "TARGET_ZBS"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 4) (zero_extract:X (match_dup 2)
+                                       (const_int 1)
+                                       (zero_extend:X (match_dup 3))))
+   (set (pc) (if_then_else (match_op_dup 1 [(match_dup 4) (const_int 0)])
+                          (label_ref (match_dup 0))
+                          (pc)))])
+
 ;; ZBKC or ZBC extension
 (define_insn "riscv_clmul_<mode>"
   [(set (match_operand:X 0 "register_operand" "=r")
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext-02.c b/gcc/testsuite/gcc.target/riscv/zbs-bext-02.c
new file mode 100644 (file)
index 0000000..3f3b840
--- /dev/null
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-funroll-loops" } } */
+
+int
+foo(const long long B, int a)
+{
+  long long b = 1;    
+  for (int sq = 0; sq < 64; sq++)
+    if (B & (b << sq)) 
+      a++;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler-times "bext\t" 1 } } */
+/* { dg-final { scan-assembler-not "bset" } } */
+/* { dg-final { scan-assembler-not "and" } } */