riscv: traps_misaligned: properly sign extend value in misaligned load handler

[ Upstream commit b3510183ab7d63c71a3f5c89043d31686a76a34c ]

Add missing cast to signed long.

Signed-off-by: Andreas Schwab <schwab@suse.de>
Fixes: 956d705dd279 ("riscv: Unaligned load/store handling for M_MODE")
Tested-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/mvmikk0goil.fsf@suse.de
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index fe0ab912014baa9ce600effcb699033f1f4158b5..f3123f1d20505fcd7ae147191be0d7164f14a91c 100644 (file)
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -460,7 +460,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)
        }
 
        if (!fp)
-               SET_RD(insn, regs, val.data_ulong << shift >> shift);
+               SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift);
        else if (len == 8)
                set_f64_rd(insn, regs, val.data_u64);
        else