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arm: remove IWMMXT checks from MD files.
authorRichard Earnshaw <rearnsha@arm.com>
Mon, 28 Apr 2025 13:17:41 +0000 (14:17 +0100)
committerRichard Earnshaw <rearnsha@arm.com>
Mon, 12 May 2025 09:34:48 +0000 (10:34 +0100)
Remove the various checks for TARGET_IWMMXT{,2} and
TARGET_REALLY_IWMMXT{,2} from the remaining machine description files.
These flags can never be true now.

gcc/ChangeLog:

* config/arm/arm.md(attr arch): Remove iwmmxt and iwmmxt2.
Remove checks based on TARGET_REALLY_IWMMXT2 from all split
patterns.
(arm_movdi): Likewise.
(*arm_movt): Likewise.
(arch_enabled): Remove test for iwmmxt2.
* config/arm/constraints.md (y, z): Remove register constraints.
(Uy): Remove memory constraint.
* config/arm/thumb2.md (thumb2_pop_single): Remove check for
IWMMXT.
* config/arm/vec-common.md (mov<mode>): Remove check for IWMMXT.
(mul<mode>3): Likewise.
(xor<mode>3): Likewise.
(<absneg_str><mode>2): Likewise.
(@movmisalign<mode>): Likewise.
(@mve_<mve_insn>q_<supf><mode>): Likewise.
(vashl<mode>3): Likewise.
(vashr<mode>3): Likewise.
(vlshr<mode>3): Likewise.
(uavg<mode>3_ceil): Likewise.

gcc/config/arm/arm.md patch | blob | blame | history
gcc/config/arm/constraints.md patch | blob | blame | history
gcc/config/arm/thumb2.md patch | blob | blame | history
gcc/config/arm/vec-common.md patch | blob | blame | history

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index af0564c36a9b05637c4fd5c05f4d14207ffe7d3f..ce1b987b24155553c922324882d056dd504a85fe 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -149,7 +149,7 @@
 ; This attribute is used to compute attribute "enabled",
 ; use type "any" to enable an alternative in all cases.
 (define_attr "arch" "any, a, t, 32, t1, t2, v6,nov6, v6t2, \
-                    v8mb, fix_vlldm, iwmmxt, iwmmxt2, armv6_or_vfpv3, \
+                    v8mb, fix_vlldm, armv6_or_vfpv3, \
                     neon, mve"
   (const_string "any"))
 
@@ -197,10 +197,6 @@
              (match_test "fix_vlldm"))
         (const_string "yes")
 
-        (and (eq_attr "arch" "iwmmxt2")
-             (match_test "TARGET_REALLY_IWMMXT2"))
-        (const_string "yes")
-
         (and (eq_attr "arch" "armv6_or_vfpv3")
              (match_test "arm_arch6 || TARGET_VFP3"))
         (const_string "yes")
@@ -2893,14 +2889,12 @@
 ;; Split DImode and, ior, xor operations.  Simply perform the logical
 ;; operation on the upper and lower halves of the registers.
 ;; This is needed for atomic operations in arm_split_atomic_op.
-;; Avoid splitting IWMMXT instructions.
 (define_split
   [(set (match_operand:DI 0 "s_register_operand" "")
        (match_operator:DI 6 "logical_binary_operator"
          [(match_operand:DI 1 "s_register_operand" "")
           (match_operand:DI 2 "s_register_operand" "")]))]
-  "TARGET_32BIT && reload_completed
-   && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
+  "TARGET_32BIT && reload_completed"
   [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)]))
    (set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4) (match_dup 5)]))]
   "
@@ -6345,7 +6339,6 @@
   "TARGET_32BIT
    && !(TARGET_HARD_FLOAT)
    && !(TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT)
-   && !TARGET_IWMMXT
    && (   register_operand (operands[0], DImode)
        || register_operand (operands[1], DImode))"
   "*
@@ -6554,7 +6547,7 @@
 (define_insn "*arm_movsi_insn"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m")
        (match_operand:SI 1 "general_operand"      "rk, I,K,j,mi,rk"))]
-  "TARGET_ARM && !TARGET_IWMMXT && !TARGET_HARD_FLOAT
+  "TARGET_ARM && !TARGET_HARD_FLOAT
    && (   register_operand (operands[0], SImode)
        || register_operand (operands[1], SImode))"
   "@
@@ -13123,7 +13116,7 @@
   [(set_attr "conds" "unconditional")
    (set_attr "type" "nop")])
 
-;; Vector bits common to IWMMXT, Neon and MVE
+;; Vector bits common to Neon and MVE
 (include "vec-common.md")
 ;; Load the VFP co-processor patterns
 (include "vfp.md")
diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md
index 9f1a37aa5d49659d58bb631f0125924f3be15702..24743a82356b3a47140c46983d765674afbb6986 100644 (file)
--- a/gcc/config/arm/constraints.md
+++ b/gcc/config/arm/constraints.md
@@ -19,11 +19,12 @@
 ;; <http://www.gnu.org/licenses/>.
 
 ;; The following register constraints have been used:
-;; - in ARM/Thumb-2 state: t, w, x, y, z
+;; - in ARM/Thumb-2 state: t, w, x
 ;; - in Thumb state: h, b
 ;; - in both states: l, c, k, q, Cs, Ts, US
 ;; In ARM state, 'l' is an alias for 'r'
 ;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
+;; 'y' and 'z' were previously used for iWMMX registers (removed after gcc-15)
 
 ;; The following normal constraints have been used:
 ;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
@@ -39,7 +40,7 @@
 ;; in all states: Pg
 
 ;; The following memory constraints have been used:
-;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us, Uo, Up, Uf, Ux, Ul, Uz
+;; in ARM/Thumb-2 state: Uh, Ut, Uv, Un, Um, Us, Uo, Up, Uf, Ux, Ul, Uz
 ;; in ARM state: Uq
 ;; in Thumb state: Uu, Uw
 ;; in all states: Q
@@ -112,13 +113,6 @@
 (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
  "The VFP registers @code{d0}-@code{d7}.")
 
-(define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
- "The Intel iWMMX co-processor registers.")
-
-(define_register_constraint "z"
- "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
- "The Intel iWMMX GR registers.")
-
 (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
  "In Thumb state the core registers @code{r0}-@code{r7}.")
 
@@ -478,12 +472,6 @@
                    ? arm_coproc_mem_operand_no_writeback (op)
                    : neon_vector_mem_operand (op, 2, true)")))
 
-(define_memory_constraint "Uy"
- "@internal
-  In ARM/Thumb-2 state a valid iWMMX load/store address."
- (and (match_code "mem")
-      (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
-
 (define_memory_constraint "Un"
  "@internal
   In ARM/Thumb-2 state a valid address for Neon doubleword vector
diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index 172c974b3dacf27ff6d7259765d7f12f3dc5affe..019f9d438c08fd68725d1da6bc2af358d06223c7 100644 (file)
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -235,7 +235,7 @@
 (define_insn "*thumb2_movsi_insn"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,lk*r,m")
        (match_operand:SI 1 "general_operand"      "rk,I,Py,K,j,mi,lk*r"))]
-  "TARGET_THUMB2 && !TARGET_IWMMXT && !TARGET_HARD_FLOAT
+  "TARGET_THUMB2 && !TARGET_HARD_FLOAT
    && (   register_operand (operands[0], SImode)
        || register_operand (operands[1], SImode))"
 {
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index a485d057f0f1fa9e4ecf392479b34df4080f962e..061165ea1cadc20f81b5bdbebbd7a3cc300bfb73 100644 (file)
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -1,4 +1,4 @@
-;; Machine Description for shared bits common to IWMMXT and Neon.
+;; Machine Description for shared bits common to Neon and MVE.
 ;; Copyright (C) 2006-2025 Free Software Foundation, Inc.
 ;; Written by CodeSourcery.
 ;;
@@ -24,7 +24,6 @@
   [(set (match_operand:VNIM1 0 "nonimmediate_operand")
        (match_operand:VNIM1 1 "general_operand"))]
   "TARGET_NEON
-   || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))
    || (TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
    || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
    {
@@ -46,8 +45,7 @@
 (define_expand "mov<mode>"
   [(set (match_operand:VNINOTM1 0 "nonimmediate_operand")
        (match_operand:VNINOTM1 1 "general_operand"))]
-  "TARGET_NEON
-   || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
+  "TARGET_NEON"
 {
   gcc_checking_assert (aligned_operand (operands[0], <MODE>mode));
   gcc_checking_assert (aligned_operand (operands[1], <MODE>mode));
@@ -83,7 +81,7 @@
 })
 
 ;; Vector arithmetic.  Expanders are blank, then unnamed insns implement
-;; patterns separately for Neon, IWMMXT and MVE.
+;; patterns separately for Neon and MVE.
 
 (define_expand "add<mode>3"
   [(set (match_operand:VDQ 0 "s_register_operand")
@@ -103,10 +101,7 @@
   [(set (match_operand:VDQWH 0 "s_register_operand")
        (mult:VDQWH (match_operand:VDQWH 1 "s_register_operand")
                    (match_operand:VDQWH 2 "s_register_operand")))]
-  "ARM_HAVE_<MODE>_ARITH
-   && (!TARGET_REALLY_IWMMXT
-       || <MODE>mode == V4HImode
-       || <MODE>mode == V2SImode)"
+  "ARM_HAVE_<MODE>_ARITH"
 )
 
 (define_expand "smin<mode>3"
@@ -216,13 +211,13 @@
 (define_expand "one_cmpl<mode>2"
   [(set (match_operand:VDQ 0 "s_register_operand")
        (not:VDQ (match_operand:VDQ 1 "s_register_operand")))]
-  "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT"
+  "ARM_HAVE_<MODE>_ARITH"
 )
 
 (define_expand "<absneg_str><mode>2"
   [(set (match_operand:VDQWH 0 "s_register_operand" "")
        (ABSNEG:VDQWH (match_operand:VDQWH 1 "s_register_operand" "")))]
-  "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT"
+  "ARM_HAVE_<MODE>_ARITH"
 )
 
 (define_expand "cadd<rot><mode>3"
@@ -295,8 +290,7 @@
  [(set (match_operand:VDQ 0 "nonimmediate_operand")
        (unspec:VDQ [(match_operand:VDQ 1 "general_operand")]
         UNSPEC_MISALIGNED_ACCESS))]
- "ARM_HAVE_<MODE>_LDST && !BYTES_BIG_ENDIAN
-  && unaligned_access && !TARGET_REALLY_IWMMXT"
+ "ARM_HAVE_<MODE>_LDST && !BYTES_BIG_ENDIAN && unaligned_access"
 {
   rtx *memloc;
   bool for_store = false;
@@ -373,7 +367,7 @@
        (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w,w")
                       (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Ds")]
         VSHLQ))]
-  "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT"
+  "ARM_HAVE_<MODE>_ARITH"
   "@
    <mve_insn>.<supf>%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2
    * return neon_output_shift_immediate (\"vshl\", 'i', &operands[2], <MODE>mode, VALID_NEON_QREG_MODE (<MODE>mode), true);"
@@ -385,7 +379,7 @@
   [(set (match_operand:VDQIW 0 "s_register_operand" "")
        (ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "")
                      (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "")))]
-  "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT"
+  "ARM_HAVE_<MODE>_ARITH"
 {
   emit_insn (gen_mve_vshlq_u<mode> (operands[0], operands[1], operands[2]));
   DONE;
@@ -398,7 +392,7 @@
   [(set (match_operand:VDQIW 0 "s_register_operand")
        (ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand")
                        (match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))]
-  "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT"
+  "ARM_HAVE_<MODE>_ARITH"
 {
   if (s_register_operand (operands[2], <MODE>mode))
     {
@@ -416,7 +410,7 @@
   [(set (match_operand:VDQIW 0 "s_register_operand")
        (lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand")
                        (match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))]
-  "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT"
+  "ARM_HAVE_<MODE>_ARITH"
 {
   if (s_register_operand (operands[2], <MODE>mode))
     {
@@ -606,8 +600,7 @@
 (define_expand "clz<mode>2"
  [(set (match_operand:VDQIW 0 "s_register_operand")
        (clz:VDQIW (match_operand:VDQIW 1 "s_register_operand")))]
-  "ARM_HAVE_<MODE>_ARITH
-   && !TARGET_REALLY_IWMMXT"
+  "ARM_HAVE_<MODE>_ARITH"
 )
 (define_expand "vec_init<mode><V_elem_l>"
   [(match_operand:VDQX 0 "s_register_operand")
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