irqchip/gic-v5: Check if impl is virt capable

Now that there is support for creating a GICv5-based guest with KVM,
check that the hardware itself supports virtualisation, skipping the
setting of struct gic_kvm_info if not.

Note: If native GICv5 virt is not supported, then nor is
FEAT_GCIE_LEGACY, so we are able to skip altogether.

Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20260128175919.3828384-33-sascha.bischoff@arm.com
[maz: cosmetic changes]
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/drivers/irqchip/irq-gic-v5-irs.c b/drivers/irqchip/irq-gic-v5-irs.c
index ce2732d649a3e9d2200d7e03a5fbc87d031e293d..eeeb40fb0eaa04cfe3c776df8135273b9766bfd3 100644 (file)
--- a/drivers/irqchip/irq-gic-v5-irs.c
+++ b/drivers/irqchip/irq-gic-v5-irs.c
@@ -743,6 +743,8 @@ static int __init gicv5_irs_init(struct device_node *node)
         * be consistent across IRSes by the architecture.
         */
        if (list_empty(&irs_nodes)) {
+               idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR0);
+               gicv5_global_data.virt_capable = !FIELD_GET(GICV5_IRS_IDR0_VIRT, idr);
 
                idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR1);
                irs_setup_pri_bits(idr);

diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c
index 41ef286c4d78122b7a2130d7f00f6c2c782216cc..3c86bbc057615895928ffe26d606f92978eb9872 100644 (file)
--- a/drivers/irqchip/irq-gic-v5.c
+++ b/drivers/irqchip/irq-gic-v5.c
@@ -1064,6 +1064,16 @@ static struct gic_kvm_info gic_v5_kvm_info __initdata;
 
 static void __init gic_of_setup_kvm_info(struct device_node *node)
 {
+       /*
+        * If we don't have native GICv5 virtualisation support, then
+        * we also don't have FEAT_GCIE_LEGACY - the architecture
+        * forbids this combination.
+        */
+       if (!gicv5_global_data.virt_capable) {
+               pr_info("GIC implementation is not virtualization capable\n");
+               return;
+       }
+
        gic_v5_kvm_info.type = GIC_V5;
 
        /* GIC Virtual CPU interface maintenance interrupt */

diff --git a/include/linux/irqchip/arm-gic-v5.h b/include/linux/irqchip/arm-gic-v5.h
index 68ddcdb1cec5a55dc8d2a7edc3ffe90b74bcf05c..4cb71ce6e8ad845ff5d3e8894e2f11fddd18464e 100644 (file)
--- a/include/linux/irqchip/arm-gic-v5.h
+++ b/include/linux/irqchip/arm-gic-v5.h
@@ -43,6 +43,7 @@
 /*
  * IRS registers and tables structures
  */
+#define GICV5_IRS_IDR0                 0x0000
 #define GICV5_IRS_IDR1                 0x0004
 #define GICV5_IRS_IDR2                 0x0008
 #define GICV5_IRS_IDR5                 0x0014
@@ -63,6 +64,8 @@
 #define GICV5_IRS_IST_STATUSR          0x0194
 #define GICV5_IRS_MAP_L2_ISTR          0x01c0
 
+#define GICV5_IRS_IDR0_VIRT            BIT(6)
+
 #define GICV5_IRS_IDR1_PRIORITY_BITS   GENMASK(22, 20)
 #define GICV5_IRS_IDR1_IAFFID_BITS     GENMASK(19, 16)
 
@@ -278,6 +281,7 @@ struct gicv5_chip_data {
        u8                      cpuif_pri_bits;
        u8                      cpuif_id_bits;
        u8                      irs_pri_bits;
+       bool                    virt_capable;
        struct {
                __le64 *l1ist_addr;
                u32 l2_size;