arm64: dts: qcom: sm8550: add missing cpu-cfg interconnect path in the mdss node

The bindings requires the mdp0-mem and the cpu-cfg interconnect path,
add the missing cpu-cfg path to fix the dtbs check error and also to ensure
that MDSS has enough bandwidth to let HLOS write config registers.

Fixes: b8591df49cde ("arm64: dts: qcom: sm8550: correct MDSS interconnects")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250227-topic-sm8x50-mdss-interconnect-bindings-fix-v5-1-bf6233c6ebe5@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index d02d80d731b9a8746655af6da236307760a8f662..18bcb4ac6bd8433a0f10f4826f4c6958444c080f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3355,8 +3355,10 @@
                        power-domains = <&dispcc MDSS_GDSC>;
 
                        interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
-                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
-                       interconnect-names = "mdp0-mem";
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+                                       <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       interconnect-names = "mdp0-mem", "cpu-cfg";
 
                        iommus = <&apps_smmu 0x1c00 0x2>;