bool __attribute__((unused)) mte = \
MTE_ENABLED (); \
bool __attribute__((unused)) sve = \
- GLRO(dl_aarch64_cpu_features).sve; \
- bool __attribute__((unused)) morello = \
- GLRO(dl_hwcap2) & HWCAP2_MORELLO;
+ GLRO(dl_aarch64_cpu_features).sve;
/* Check if SVE is supported. */
cpu_features->sve = GLRO (dl_hwcap) & HWCAP_SVE;
-
- /* Check if Morello is supported. */
- cpu_features->morello = GLRO (dl_hwcap2) & HWCAP2_MORELLO;
}
#define IS_A64FX(midr) (MIDR_IMPLEMENTOR(midr) == 'F' \
&& MIDR_PARTNUM(midr) == 0x001)
-/* TODO: This is based on the Morello Fast Model.
- Will MIDR_IMPLEMENTOR change to 'A'? */
-#define IS_MORELLO(midr) (MIDR_IMPLEMENTOR(midr) == 0x3f \
- && MIDR_PARTNUM(midr) == 0x412)
-
struct cpu_features
{
uint64_t midr_el1;
/* Currently, the GLIBC memory tagging tunable only defines 8 bits. */
uint8_t mte_state;
bool sve;
- bool morello;
};
#endif /* _CPU_FEATURES_AARCH64_H */