#define BMG_TELEMETRY_BASE_OFFSET 0xE0000
#define BMG_TELEMETRY_OFFSET (SOC_BASE + BMG_TELEMETRY_BASE_OFFSET)
-#define SG_REMAP_INDEX1 XE_REG(SOC_BASE + 0x08)
-#define SG_REMAP_BITS REG_GENMASK(31, 24)
-
#define BMG_MODS_RESIDENCY_OFFSET (0x4D0)
#define BMG_G2_RESIDENCY_OFFSET (0x530)
#define BMG_G6_RESIDENCY_OFFSET (0x538)
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+#ifndef _XE_SOC_REMAPPER_REGS_H_
+#define _XE_SOC_REMAPPER_REGS_H_
+
+#include "xe_regs.h"
+
+#define SG_REMAP_INDEX1 XE_REG(SOC_BASE + 0x08)
+#define SG_REMAP_TELEM_MASK REG_GENMASK(31, 24)
+
+#endif
u8 has_pxp:1;
/** @info.has_range_tlb_inval: Has range based TLB invalidations */
u8 has_range_tlb_inval:1;
+ /** @info.has_soc_remapper_telem: Has SoC remapper telemetry support */
+ u8 has_soc_remapper_telem:1;
/** @info.has_sriov: Supports SR-IOV */
u8 has_sriov:1;
/** @info.has_usm: Device has unified shared memory support */
struct {
/** @soc_remapper.lock: Serialize access to SoC Remapper's index registers */
spinlock_t lock;
+
+ /** @soc_remapper.set_telem_region: Set telemetry index */
+ void (*set_telem_region)(struct xe_device *xe, u32 index);
} soc_remapper;
/**
.has_i2c = true,
.has_late_bind = true,
.has_pre_prod_wa = 1,
+ .has_soc_remapper_telem = true,
.has_sriov = true,
.has_mem_copy_instr = true,
.max_gt_per_tile = 2,
.has_mbx_power_limits = true,
.has_mert = true,
.has_pre_prod_wa = 1,
+ .has_soc_remapper_telem = true,
.has_sriov = true,
.max_gt_per_tile = 2,
.require_force_probe = true,
xe->info.has_page_reclaim_hw_assist = desc->has_page_reclaim_hw_assist;
xe->info.has_pre_prod_wa = desc->has_pre_prod_wa;
xe->info.has_pxp = desc->has_pxp;
+ xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
desc->has_sriov;
xe->info.has_mem_copy_instr = desc->has_mem_copy_instr;
u8 has_pre_prod_wa:1;
u8 has_page_reclaim_hw_assist:1;
u8 has_pxp:1;
+ u8 has_soc_remapper_telem:1;
u8 has_sriov:1;
u8 needs_scratch:1;
u8 skip_guc_pc:1;
* Copyright © 2025 Intel Corporation
*/
+#include "regs/xe_soc_remapper_regs.h"
+#include "xe_mmio.h"
#include "xe_soc_remapper.h"
+static void xe_soc_remapper_set_region(struct xe_device *xe, struct xe_reg reg,
+ u32 mask, u32 val)
+{
+ guard(spinlock_irqsave)(&xe->soc_remapper.lock);
+ xe_mmio_rmw32(xe_root_tile_mmio(xe), reg, mask, val);
+}
+
+static void xe_soc_remapper_set_telem_region(struct xe_device *xe, u32 index)
+{
+ xe_soc_remapper_set_region(xe, SG_REMAP_INDEX1, SG_REMAP_TELEM_MASK,
+ REG_FIELD_PREP(SG_REMAP_TELEM_MASK, index));
+}
+
/**
* xe_soc_remapper_init() - Initialize SoC remapper
* @xe: Pointer to xe device.
*/
int xe_soc_remapper_init(struct xe_device *xe)
{
- spin_lock_init(&xe->soc_remapper.lock);
+ if (xe->info.has_soc_remapper_telem) {
+ spin_lock_init(&xe->soc_remapper.lock);
+ xe->soc_remapper.set_telem_region = xe_soc_remapper_set_telem_region;
+ }
return 0;
}
guard(mutex)(&xe->pmt.lock);
+ if (!xe->soc_remapper.set_telem_region)
+ return -ENODEV;
+
/* indicate that we are not at an appropriate power level */
if (!xe_pm_runtime_get_if_active(xe))
return -ENODATA;
/* set SoC re-mapper index register based on GUID memory region */
- xe_mmio_rmw32(xe_root_tile_mmio(xe), SG_REMAP_INDEX1, SG_REMAP_BITS,
- REG_FIELD_PREP(SG_REMAP_BITS, mem_region));
+ xe->soc_remapper.set_telem_region(xe, mem_region);
memcpy_fromio(data, telem_addr, count);
xe_pm_runtime_put(xe);