perf/x86/intel: Update event constraints and cache_extra_regsfor LNL

Update perf hard-coded event constraints and cache_extra_regs[] for
Lunarlake according to the latest LNL perfmon events (V1.22).

LNL introduces new extra register values for the OCR L3 cache events,
so introduce lnc_hw_cache_extra_regs[] and skt_hw_cache_extra_regs[] to
reflect the changes.

LNL perfmon events:
https://github.com/intel/perfmon/blob/main/LNL/events/lunarlake_lioncove_core.json
https://github.com/intel/perfmon/blob/main/LNL/events/lunarlake_skymont_core.json

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260515061143.338553-7-dapeng1.mi@linux.intel.com

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 81619127ef04aa1b479813e27783f85cca1aeaa0..dc0991cee8c69d8236d78f0f5cbaecf38c74e7f3 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -225,12 +225,17 @@ static struct event_constraint intel_grt_event_constraints[] __read_mostly = {
 
 static struct event_constraint intel_skt_event_constraints[] __read_mostly = {
        FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
+       FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
        FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-       FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
+       FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
+       FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
        FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
        FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
+       FIXED_EVENT_CONSTRAINT(0x0500, 4), /* pseudo TOPDOWN_BAD_SPECULATION.ALL */
        FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
+       FIXED_EVENT_CONSTRAINT(0x0600, 5), /* pseudo TOPDOWN_FE_BOUND.ALL */
        FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
+       FIXED_EVENT_CONSTRAINT(0x0700, 6), /* pseudo TOPDOWN_RETIRING.ALL */
        EVENT_CONSTRAINT_END
 };
 
@@ -415,11 +420,12 @@ static struct extra_reg intel_rwc_extra_regs[] __read_mostly = {
 
 static struct event_constraint intel_lnc_event_constraints[] = {
        FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
-       FIXED_EVENT_CONSTRAINT(0x0100, 0),      /* INST_RETIRED.PREC_DIST */
+       FIXED_EVENT_CONSTRAINT(0x0100, 0),      /* pseudo INST_RETIRED.ANY */
        FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
-       FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
+       FIXED_EVENT_CONSTRAINT(0x0200, 1),      /* pseudo CPU_CLK_UNHALTED.THREAD */
+       FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* pseudo CPU_CLK_UNHALTED.REF_TSC */
        FIXED_EVENT_CONSTRAINT(0x013c, 2),      /* CPU_CLK_UNHALTED.REF_TSC_P */
-       FIXED_EVENT_CONSTRAINT(0x0400, 3),      /* SLOTS */
+       FIXED_EVENT_CONSTRAINT(0x0400, 3),      /* pseudo TOPDOWN.SLOTS */
        METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
        METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
        METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
@@ -431,8 +437,6 @@ static struct event_constraint intel_lnc_event_constraints[] = {
 
        INTEL_EVENT_CONSTRAINT(0x20, 0xf),
 
-       INTEL_UEVENT_CONSTRAINT(0x012a, 0xf),
-       INTEL_UEVENT_CONSTRAINT(0x012b, 0xf),
        INTEL_UEVENT_CONSTRAINT(0x0148, 0x4),
        INTEL_UEVENT_CONSTRAINT(0x0175, 0x4),
 
@@ -443,15 +447,14 @@ static struct event_constraint intel_lnc_event_constraints[] = {
        INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
        INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
        INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
-       INTEL_UEVENT_CONSTRAINT(0x10a4, 0x1),
+       INTEL_UEVENT_CONSTRAINT(0x10a4, 0x8),
        INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
        INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc),
        INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),
 
+       INTEL_UEVENT_CONSTRAINT(0x87d0, 0x3ff),
        INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
 
-       INTEL_UEVENT_CONSTRAINT(0x00e0, 0xf),
-
        EVENT_CONSTRAINT_END
 };
 
@@ -830,6 +833,23 @@ static __initconst const u64 adl_glc_hw_cache_extra_regs
  },
 };
 
+static __initconst const u64 lnc_hw_cache_extra_regs
+                               [PERF_COUNT_HW_CACHE_MAX]
+                               [PERF_COUNT_HW_CACHE_OP_MAX]
+                               [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+ [ C(LL  ) ] = {
+       [ C(OP_READ) ] = {
+               [ C(RESULT_ACCESS) ] = 0x10001,         /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
+               [ C(RESULT_MISS)   ] = 0x9E7FA000001,   /* OCR.DEMAND_DATA_RD.L3_MISS */
+       },
+       [ C(OP_WRITE) ] = {
+               [ C(RESULT_ACCESS) ] = 0x10002,         /* OCR.DEMAND_RFO.ANY_RESPONSE */
+               [ C(RESULT_MISS)   ] = 0x9E7FA000002,   /* OCR.DEMAND_RFO.L3_MISS */
+       },
+ },
+};
+
 static __initconst const u64 pnc_hw_cache_event_ids
                                [PERF_COUNT_HW_CACHE_MAX]
                                [PERF_COUNT_HW_CACHE_OP_MAX]
@@ -2510,6 +2530,22 @@ static __initconst const u64 cmt_hw_cache_extra_regs
        },
 };
 
+static __initconst const u64 skt_hw_cache_extra_regs
+                               [PERF_COUNT_HW_CACHE_MAX]
+                               [PERF_COUNT_HW_CACHE_OP_MAX]
+                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+       [C(LL)] = {
+               [C(OP_READ)] = {
+                       [C(RESULT_ACCESS)]      = 0x10001,              /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
+                       [C(RESULT_MISS)]        = 0x13FBFC00001,        /* OCR.DEMAND_DATA_RD.L3_MISS */
+               },
+               [C(OP_WRITE)] = {
+                       [C(RESULT_ACCESS)]      = 0x10002,              /* OCR.DEMAND_RFO.ANY_RESPONSE */
+                       [C(RESULT_MISS)]        = 0x13FBFC00002,        /* OCR.DEMAND_RFO.L3_MISS */
+               },
+       },
+};
+
 static __initconst const u64 arw_hw_cache_extra_regs
                                [PERF_COUNT_HW_CACHE_MAX]
                                [PERF_COUNT_HW_CACHE_OP_MAX]
@@ -7707,6 +7743,9 @@ static __always_inline void intel_pmu_init_lnc(struct pmu *pmu)
        hybrid(pmu, event_constraints) = intel_lnc_event_constraints;
        hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints;
        hybrid(pmu, extra_regs) = intel_lnc_extra_regs;
+
+       memcpy(hybrid_var(pmu, hw_cache_event_ids), adl_glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
+       memcpy(hybrid_var(pmu, hw_cache_extra_regs), lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
 }
 
 static __always_inline void intel_pmu_init_pnc(struct pmu *pmu)
@@ -7726,9 +7765,10 @@ static __always_inline void intel_pmu_init_pnc(struct pmu *pmu)
 
 static __always_inline void intel_pmu_init_skt(struct pmu *pmu)
 {
-       intel_pmu_init_grt(pmu);
+       intel_pmu_init_cmt(pmu);
        hybrid(pmu, event_constraints) = intel_skt_event_constraints;
-       hybrid(pmu, extra_regs) = intel_cmt_extra_regs;
+       memcpy(hybrid_var(pmu, hw_cache_extra_regs),
+              skt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
        static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
 }
 

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 75b7f6f6d8bc54f93b3ad650fe4bffb555f8a9a1..ce23b50f449add56e79533451a2c8ff2402e17eb 100644 (file)
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -1507,6 +1507,13 @@ struct event_constraint intel_lnc_pebs_event_constraints[] = {
        INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL),   /* INST_RETIRED.PREC_DIST */
        INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
 
+       INTEL_FLAGS_UEVENT_CONSTRAINT(0x012a, 0x1),             /* OCR.* events */
+       INTEL_FLAGS_UEVENT_CONSTRAINT(0x012b, 0x1),             /* OCR.* events */
+
+       INTEL_FLAGS_UEVENT_CONSTRAINT(0x04a4, 0x1),             /* TOPDOWN.BAD_SPEC_SLOTS */
+       INTEL_FLAGS_UEVENT_CONSTRAINT(0x08a4, 0x1),             /* TOPDOWN.BR_MISPREDICT_SLOTS */
+       INTEL_FLAGS_UEVENT_CONSTRAINT(0x10a4, 0x8),             /* TOPDOWN.MEMORY_BOUND_SLOTS */
+
        INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0x3fc),
        INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3),
        INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf),   /* MEM_INST_RETIRED.STLB_MISS_LOADS */
@@ -1516,6 +1523,7 @@ struct event_constraint intel_lnc_pebs_event_constraints[] = {
        INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf),   /* MEM_INST_RETIRED.SPLIT_STORES */
        INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf),   /* MEM_INST_RETIRED.ALL_LOADS */
        INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf),   /* MEM_INST_RETIRED.ALL_STORES */
+       INTEL_FLAGS_UEVENT_CONSTRAINT(0x87d0, 0x3ff),           /* MEM_INST_RETIRED.ANY */
 
        INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),