arm64: dts: qcom: qcs8300: add Display Serial Interface device nodes

Add device tree nodes for the DSI0 controller with their corresponding
PHY found on Qualcomm QCS8300 SoC.

Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260217090955.2446470-2-quic_amakhija@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index fcf765267f8209777f83088e5fcaff58f3f89f1c..8b2b17530bd8424b25aebfdab14b69eacb6aff4d 100644 (file)
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -3,6 +3,7 @@
  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
 #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
@@ -5596,9 +5597,19 @@
                                                reg = <0>;
 
                                                dpu_intf0_out: endpoint {
+
                                                        remote-endpoint = <&mdss_dp0_in>;
                                                };
                                        };
+
+                                       port@1 {
+                                               reg = <1>;
+
+                                               dpu_intf1_out: endpoint {
+
+                                                       remote-endpoint = <&mdss_dsi0_in>;
+                                               };
+                                       };
                                };
 
                                mdp_opp_table: opp-table {
@@ -5626,6 +5637,98 @@
                                };
                        };
 
+                       mdss_dsi0: dsi@ae94000 {
+                               compatible = "qcom,qcs8300-dsi-ctrl",
+                                            "qcom,sa8775p-dsi-ctrl",
+                                            "qcom,mdss-dsi-ctrl";
+                               reg = <0x0 0x0ae94000 0x0 0x400>;
+                               reg-names = "dsi_ctrl";
+
+                               interrupt-parent = <&mdss>;
+                               interrupts = <4>;
+
+                               clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
+                                        <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
+                                        <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
+                                        <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
+                                        <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+                                        <&gcc GCC_DISP_HF_AXI_CLK>;
+                               clock-names = "byte",
+                                             "byte_intf",
+                                             "pixel",
+                                             "core",
+                                             "iface",
+                                             "bus";
+
+                               assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
+                                                 <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
+                               assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+                                                        <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
+
+                               phys = <&mdss_dsi0_phy>;
+
+                               operating-points-v2 = <&mdss_dsi_opp_table>;
+                               power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+                               refgen-supply = <&refgen>;
+
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+
+                                               mdss_dsi0_in: endpoint {
+
+                                                       remote-endpoint = <&dpu_intf1_out>;
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+
+                                               mdss_dsi0_out: endpoint {
+                                               };
+                                       };
+                               };
+
+                               mdss_dsi_opp_table: opp-table {
+                                       compatible = "operating-points-v2";
+
+                                       opp-358000000 {
+                                               opp-hz = /bits/ 64 <358000000>;
+                                               required-opps = <&rpmhpd_opp_svs_l1>;
+                                       };
+                               };
+                       };
+
+                       mdss_dsi0_phy: phy@ae94400 {
+                               compatible = "qcom,qcs8300-dsi-phy-5nm",
+                                            "qcom,sa8775p-dsi-phy-5nm";
+                               reg = <0x0 0x0ae94400 0x0 0x200>,
+                                     <0x0 0x0ae94600 0x0 0x280>,
+                                     <0x0 0x0ae94900 0x0 0x280>;
+                               reg-names = "dsi_phy",
+                                           "dsi_phy_lane",
+                                           "dsi_pll";
+
+                               #clock-cells = <1>;
+                               #phy-cells = <0>;
+
+                               clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+                                        <&rpmhcc RPMH_CXO_CLK>;
+                               clock-names = "iface",
+                                             "ref";
+
+                               status = "disabled";
+                       };
+
                        mdss_dp0_phy: phy@aec2a00 {
                                compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";
 
@@ -5753,7 +5856,9 @@
                                 <&mdss_dp0_phy 0>,
                                 <&mdss_dp0_phy 1>,
                                 <0>, <0>,
-                                <0>, <0>, <0>, <0>;
+                                <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+                                <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
+                                <0>, <0>;
                        power-domains = <&rpmhpd RPMHPD_MMCX>;
                        #clock-cells = <1>;
                        #reset-cells = <1>;