]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
arm64: dts: ti: k3-am62p: fix pinctrl settings
authorMichael Walle <mwalle@kernel.org>
Fri, 21 Feb 2025 09:14:46 +0000 (10:14 +0100)
committerVignesh Raghavendra <vigneshr@ti.com>
Wed, 5 Mar 2025 04:16:09 +0000 (09:46 +0530)
It appears that pinctrl-single is misused on this SoC to control both
the mux and the input and output and bias settings. This results in
non-working pinctrl configurations for GPIOs within the device tree.

This is what happens:
 (1) During startup the pinctrl settings are applied according to the
     device tree. I.e. the pin is configured as output and with
     pull-ups enabled.
 (2) During startup a device driver requests a GPIO.
 (3) pinctrl-single is applying the default GPIO setting according to
     the pinctrl-single,gpio-range property.

This would work as expected if the pinctrl-single is only controlling
the function mux, but it also controls the input/output buffer enable,
the pull-up and pull-down settings etc (pinctrl-single,function-mask
covers the entire pad setting instead of just the mux field).

Remove the pinctrl-single,gpio-range property, so that no settings are
applied during a gpio_request() call.

Fixes: d72d73a44c3c ("arm64: dts: ti: k3-am62p: Add gpio-ranges properties")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Link: https://lore.kernel.org/r/20250221091447.595199-1-mwalle@kernel.org
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
arch/arm64/boot/dts/ti/k3-am62p-main.dtsi

index b33aff0d65c9def755f8dda9eb9feda7bc74e5c8..bd6a00d13aea758ac71c85e5958c8f171abfb6ec 100644 (file)
                #pinctrl-cells = <1>;
                pinctrl-single,register-width = <32>;
                pinctrl-single,function-mask = <0xffffffff>;
-               pinctrl-single,gpio-range =
-                       <&mcu_pmx_range 0 21 PIN_GPIO_RANGE_IOPAD>,
-                       <&mcu_pmx_range 23 1 PIN_GPIO_RANGE_IOPAD>,
-                       <&mcu_pmx_range 32 2 PIN_GPIO_RANGE_IOPAD>;
                bootph-all;
-
-               mcu_pmx_range: gpio-range {
-                       #pinctrl-single,gpio-range-cells = <3>;
-               };
        };
 
        mcu_esm: esm@4100000 {
index 4b47b07743305d5ec41a1fdd1bdf4eb9c74f470f..6aea9d3f134e4bce2ea0fa71007848dbda4383e8 100644 (file)
        };
 };
 
-&main_pmx0 {
-       pinctrl-single,gpio-range =
-               <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>,
-               <&main_pmx0_range 33 38 PIN_GPIO_RANGE_IOPAD>,
-               <&main_pmx0_range 72 22 PIN_GPIO_RANGE_IOPAD>,
-               <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>,
-               <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>,
-               <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>;
-
-       main_pmx0_range: gpio-range {
-               #pinctrl-single,gpio-range-cells = <3>;
-       };
-};
-
 &main_gpio0 {
        gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
                        <&main_pmx0 70 72 22>;