perf arm_spe: Fix memset subclass in operation

The operation subclass is extracted from bits [7..1] of the payload.
Since bit [0] is not parsed, there is no chance to match the memset type
(0x25). As a result, the memset payload is never parsed successfully.

Instead of extracting a unified bit field, change to extract the
specific bits for each operation subclass.

Fixes: 34fb60400e32 ("perf arm-spe: Add raw decoding for SPEv1.3 MTE and MOPS load/store")
Signed-off-by: Leo Yan <leo.yan@arm.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Reviewed-by: James Clark <james.clark@linaro.org>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>

diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
index 80561630253dd5c46f7e99b24fc13b99f346459f..1a1ffe50ee73ab4400fd1163d0e84e54f4d8ab0b 100644 (file)
--- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
+++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
@@ -371,31 +371,20 @@ static int arm_spe_pkt_desc_op_type(const struct arm_spe_pkt *packet,
                                arm_spe_pkt_out_string(&err, &buf, &buf_len, " AR");
                }
 
-               switch (SPE_OP_PKT_LDST_SUBCLASS_GET(payload)) {
-               case SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP:
+               if (SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP(payload))
                        arm_spe_pkt_out_string(&err, &buf, &buf_len, " SIMD-FP");
-                       break;
-               case SPE_OP_PKT_LDST_SUBCLASS_GP_REG:
+               else if (SPE_OP_PKT_LDST_SUBCLASS_GP_REG(payload))
                        arm_spe_pkt_out_string(&err, &buf, &buf_len, " GP-REG");
-                       break;
-               case SPE_OP_PKT_LDST_SUBCLASS_UNSPEC_REG:
+               else if (SPE_OP_PKT_LDST_SUBCLASS_UNSPEC_REG(payload))
                        arm_spe_pkt_out_string(&err, &buf, &buf_len, " UNSPEC-REG");
-                       break;
-               case SPE_OP_PKT_LDST_SUBCLASS_NV_SYSREG:
+               else if (SPE_OP_PKT_LDST_SUBCLASS_NV_SYSREG(payload))
                        arm_spe_pkt_out_string(&err, &buf, &buf_len, " NV-SYSREG");
-                       break;
-               case SPE_OP_PKT_LDST_SUBCLASS_MTE_TAG:
+               else if (SPE_OP_PKT_LDST_SUBCLASS_MTE_TAG(payload))
                        arm_spe_pkt_out_string(&err, &buf, &buf_len, " MTE-TAG");
-                       break;
-               case SPE_OP_PKT_LDST_SUBCLASS_MEMCPY:
+               else if (SPE_OP_PKT_LDST_SUBCLASS_MEMCPY(payload))
                        arm_spe_pkt_out_string(&err, &buf, &buf_len, " MEMCPY");
-                       break;
-               case SPE_OP_PKT_LDST_SUBCLASS_MEMSET:
+               else if (SPE_OP_PKT_LDST_SUBCLASS_MEMSET(payload))
                        arm_spe_pkt_out_string(&err, &buf, &buf_len, " MEMSET");
-                       break;
-               default:
-                       break;
-               }
 
                if (SPE_OP_PKT_IS_LDST_SVE(payload)) {
                        /* SVE effective vector length */

diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
index d00c2481712dcc457eab2f5e9848ffc3150e6236..75e355fe3438cc07704cb61a66ca162bd0904042 100644 (file)
--- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
+++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
@@ -125,14 +125,13 @@ enum arm_spe_events {
 
 #define SPE_OP_PKT_IS_OTHER_SVE_OP(v)          (((v) & (BIT(7) | BIT(3) | BIT(0))) == 0x8)
 
-#define SPE_OP_PKT_LDST_SUBCLASS_GET(v)                ((v) & GENMASK_ULL(7, 1))
-#define SPE_OP_PKT_LDST_SUBCLASS_GP_REG                0x0
-#define SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP       0x4
-#define SPE_OP_PKT_LDST_SUBCLASS_UNSPEC_REG    0x10
-#define SPE_OP_PKT_LDST_SUBCLASS_NV_SYSREG     0x30
-#define SPE_OP_PKT_LDST_SUBCLASS_MTE_TAG       0x14
-#define SPE_OP_PKT_LDST_SUBCLASS_MEMCPY                0x20
-#define SPE_OP_PKT_LDST_SUBCLASS_MEMSET                0x25
+#define SPE_OP_PKT_LDST_SUBCLASS_GP_REG(v)     (((v) & GENMASK_ULL(7, 1)) == 0x0)
+#define SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP(v)    (((v) & GENMASK_ULL(7, 1)) == 0x4)
+#define SPE_OP_PKT_LDST_SUBCLASS_UNSPEC_REG(v) (((v) & GENMASK_ULL(7, 1)) == 0x10)
+#define SPE_OP_PKT_LDST_SUBCLASS_NV_SYSREG(v)  (((v) & GENMASK_ULL(7, 1)) == 0x30)
+#define SPE_OP_PKT_LDST_SUBCLASS_MTE_TAG(v)    (((v) & GENMASK_ULL(7, 1)) == 0x14)
+#define SPE_OP_PKT_LDST_SUBCLASS_MEMCPY(v)     (((v) & GENMASK_ULL(7, 1)) == 0x20)
+#define SPE_OP_PKT_LDST_SUBCLASS_MEMSET(v)     (((v) & GENMASK_ULL(7, 0)) == 0x25)
 
 #define SPE_OP_PKT_IS_LDST_ATOMIC(v)           (((v) & (GENMASK_ULL(7, 5) | BIT(1))) == 0x2)