drm/amd/display: Add missing DCCG register entries for DCN20-DCN316

Commit 4c595e75110e ("drm/amd/display: Migrate DCCG registers access
from hwseq to dccg component.") moved register writes from hwseq to
dccg2_*() functions but did not add the registers to the DCCG register
list macros. The struct fields default to 0, so REG_WRITE() targets
MMIO offset 0, causing a GPU hang on resume (seen on DCN21/DCN30
during IGT kms_cursor_crc@cursor-suspend).

Add
- MICROSECOND_TIME_BASE_DIV
- MILLISECOND_TIME_BASE_DIV
- DCCG_GATE_DISABLE_CNTL
- DCCG_GATE_DISABLE_CNTL2
- DC_MEM_GLOBAL_PWR_REQ_CNTL
to macros in  dcn20_dccg.h, dcn301_dccg.h, dcn31_dccg.h, and dcn314_dccg.h.

Fixes: 4c595e75110e ("drm/amd/display: Migrate DCCG registers access from hwseq to dccg component.")
Reported-by: Rafael Passos <rafael@rcpassos.me>
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit e6e2b956fc814de766d3480be7018297c41d3ce0)

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
index 3711d400773af1181f1da737a9066e951ffac864..4c4e61bc91b5058e01019d75999a236bb75c2410 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
@@ -38,7 +38,11 @@
        DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
        DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
        SR(DISPCLK_FREQ_CHANGE_CNTL),\
-       SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
+       SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\
+       SR(MICROSECOND_TIME_BASE_DIV),\
+       SR(MILLISECOND_TIME_BASE_DIV),\
+       SR(DCCG_GATE_DISABLE_CNTL),\
+       SR(DCCG_GATE_DISABLE_CNTL2)
 
 #define DCCG_REG_LIST_DCN2() \
        DCCG_COMMON_REG_LIST_DCN_BASE(),\

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h
index 067e49cb238ec43efee0fdb6abfa9f2386fa12bf..e2381ca0be0b433f2e8cb5efbfa9064dcffe519b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h
@@ -34,7 +34,13 @@
        DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
        DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
        DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
-       SR(REFCLK_CNTL)
+       SR(REFCLK_CNTL),\
+       SR(DISPCLK_FREQ_CHANGE_CNTL),\
+       SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\
+       SR(MICROSECOND_TIME_BASE_DIV),\
+       SR(MILLISECOND_TIME_BASE_DIV),\
+       SR(DCCG_GATE_DISABLE_CNTL),\
+       SR(DCCG_GATE_DISABLE_CNTL2)
 
 #define DCCG_MASK_SH_LIST_DCN301(mask_sh) \
        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
index bf659920d4cc2e9cee8246de322e7c9b89d90b15..b5e3849ef12a8fc813bb9c748300a58dfc3f86b9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
@@ -64,9 +64,12 @@
        SR(DSCCLK1_DTO_PARAM),\
        SR(DSCCLK2_DTO_PARAM),\
        SR(DSCCLK_DTO_CTRL),\
+       SR(DCCG_GATE_DISABLE_CNTL),\
        SR(DCCG_GATE_DISABLE_CNTL2),\
        SR(DCCG_GATE_DISABLE_CNTL3),\
-       SR(HDMISTREAMCLK0_DTO_PARAM)
+       SR(HDMISTREAMCLK0_DTO_PARAM),\
+       SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\
+       SR(MICROSECOND_TIME_BASE_DIV)
 
 
 #define DCCG_MASK_SH_LIST_DCN31(mask_sh) \

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
index a609635f35dbdd46d1f1a528f77b136b89a7fb7d..ecbdc05f7c45981f3c5128eb230c5711b5335780 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
@@ -70,11 +70,14 @@
        SR(DSCCLK2_DTO_PARAM),\
        SR(DSCCLK3_DTO_PARAM),\
        SR(DSCCLK_DTO_CTRL),\
+       SR(DCCG_GATE_DISABLE_CNTL),\
        SR(DCCG_GATE_DISABLE_CNTL2),\
        SR(DCCG_GATE_DISABLE_CNTL3),\
        SR(HDMISTREAMCLK0_DTO_PARAM),\
        SR(OTG_PIXEL_RATE_DIV),\
-       SR(DTBCLK_P_CNTL)
+       SR(DTBCLK_P_CNTL),\
+       SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\
+       SR(MICROSECOND_TIME_BASE_DIV)
 
 #define DCCG_MASK_SH_LIST_DCN314_COMMON(mask_sh) \
        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\