ARM: dts: amlogic: meson8: fix reference to unknown/untested PWM clock

Device-tree expects absent clocks to be specified as <0> (instead of
using <>). This fixes using the FCLK4/FCLK3 clocks as they are now
seen at their correct index (while before they were recognized, but at
the correct index - resulting in the hardware using a different clock
than what the kernel sees).

Fixes: 802cff460aab ("ARM: dts: amlogic: meson8: switch to the new PWM controller binding")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250420164801.330505-2-martin.blumenstingl@googlemail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi
index 847f7b1f1e9617cb8b7d153a1ae62b0ff2112606..f785e0de0847b592e58182c46778e17b1d61e870 100644 (file)
--- a/arch/arm/boot/dts/amlogic/meson8.dtsi
+++ b/arch/arm/boot/dts/amlogic/meson8.dtsi
@@ -451,7 +451,7 @@
        pwm_ef: pwm@86c0 {
                compatible = "amlogic,meson8-pwm-v2";
                clocks = <&xtal>,
-                        <>, /* unknown/untested, the datasheet calls it "Video PLL" */
+                        <0>, /* unknown/untested, the datasheet calls it "Video PLL" */
                         <&clkc CLKID_FCLK_DIV4>,
                         <&clkc CLKID_FCLK_DIV3>;
                reg = <0x86c0 0x10>;
@@ -705,7 +705,7 @@
 &pwm_ab {
        compatible = "amlogic,meson8-pwm-v2";
        clocks = <&xtal>,
-                <>, /* unknown/untested, the datasheet calls it "Video PLL" */
+                <0>, /* unknown/untested, the datasheet calls it "Video PLL" */
                 <&clkc CLKID_FCLK_DIV4>,
                 <&clkc CLKID_FCLK_DIV3>;
 };
@@ -713,7 +713,7 @@
 &pwm_cd {
        compatible = "amlogic,meson8-pwm-v2";
        clocks = <&xtal>,
-                <>, /* unknown/untested, the datasheet calls it "Video PLL" */
+                <0>, /* unknown/untested, the datasheet calls it "Video PLL" */
                 <&clkc CLKID_FCLK_DIV4>,
                 <&clkc CLKID_FCLK_DIV3>;
 };