arm64: dts: qcom: pq5332-rdp-common: Enable QPIC SPI NAND support

Enable QPIC SPI NAND flash controller support on the IPQ5332 reference
design platform.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Link: https://lore.kernel.org/r/20260306113940.1654304-5-quic_mdalam@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
index b37ae7749083f43f482231c1de9f99ac28ea2b66..8967861be5fda0e6fd9de742bf353184a609bd5c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
@@ -78,4 +78,48 @@
                drive-strength = <8>;
                bias-pull-down;
        };
+
+       qpic_snand_default_state: qpic-snand-default-state {
+               clock-pins {
+                       pins = "gpio13";
+                       function = "qspi_clk";
+                       drive-strength = <8>;
+                       bias-disable;
+               };
+
+               cs-pins {
+                       pins = "gpio12";
+                       function = "qspi_cs";
+                       drive-strength = <8>;
+                       bias-disable;
+               };
+
+               data-pins {
+                       pins = "gpio8", "gpio9", "gpio10", "gpio11";
+                       function = "qspi_data";
+                       drive-strength = <8>;
+                       bias-disable;
+               };
+       };
+};
+
+&qpic_bam {
+       status = "okay";
+};
+
+&qpic_nand {
+       pinctrl-0 = <&qpic_snand_default_state>;
+       pinctrl-names = "default";
+
+       status = "okay";
+
+       flash@0 {
+               compatible = "spi-nand";
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               nand-ecc-engine = <&qpic_nand>;
+               nand-ecc-strength = <4>;
+               nand-ecc-step-size = <512>;
+       };
 };

diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts
index ed8a54eb95c02b17827a4ca297b50e1db17f5c4f..6e2abde9ed89e6f7b6f21a29ff384fd6d8058edb 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts
@@ -35,17 +35,6 @@
        };
 };
 
-&sdhc {
-       bus-width = <4>;
-       max-frequency = <192000000>;
-       mmc-ddr-1_8v;
-       mmc-hs200-1_8v;
-       non-removable;
-       pinctrl-0 = <&sdc_default_state>;
-       pinctrl-names = "default";
-       status = "okay";
-};
-
 &tlmm {
        i2c_1_pins: i2c-1-state {
                pins = "gpio29", "gpio30";
@@ -54,29 +43,6 @@
                bias-pull-up;
        };
 
-       sdc_default_state: sdc-default-state {
-               clk-pins {
-                       pins = "gpio13";
-                       function = "sdc_clk";
-                       drive-strength = <8>;
-                       bias-disable;
-               };
-
-               cmd-pins {
-                       pins = "gpio12";
-                       function = "sdc_cmd";
-                       drive-strength = <8>;
-                       bias-pull-up;
-               };
-
-               data-pins {
-                       pins = "gpio8", "gpio9", "gpio10", "gpio11";
-                       function = "sdc_data";
-                       drive-strength = <8>;
-                       bias-pull-up;
-               };
-       };
-
        spi_0_data_clk_pins: spi-0-data-clk-state {
                pins = "gpio14", "gpio15", "gpio16";
                function = "blsp0_spi";