]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/i915/lt_phy: Remove LT PHY specific state verification
authorMika Kahola <mika.kahola@intel.com>
Thu, 12 Mar 2026 08:06:55 +0000 (08:06 +0000)
committerMika Kahola <mika.kahola@intel.com>
Tue, 24 Mar 2026 07:46:01 +0000 (09:46 +0200)
Remove LT PHY specific state verification as DPLL framework
has state verification check.

v2: Reuse intel_lt_phy_pll_compare_hw_state() as only config[0]
    and config[0] parameters are reliable with LT PHY (Suraj)
v3: Rephrase handling of LT PHY case when verifying the state (CI)
v4: Fix checkpatch warning of line length exceeding 100 columns

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260312080657.2648265-23-mika.kahola@intel.com
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
drivers/gpu/drm/i915/display/intel_lt_phy.c
drivers/gpu/drm/i915/display/intel_lt_phy.h
drivers/gpu/drm/i915/display/intel_modeset_verify.c

index 534cc691979fdacd532f9ba89532600fbe93bf35..421767dd83678309bb3828da053b0421cae541cd 100644 (file)
@@ -5075,6 +5075,7 @@ verify_single_dpll_state(struct intel_display *display,
                         const struct intel_crtc_state *new_crtc_state)
 {
        struct intel_dpll_hw_state dpll_hw_state = {};
+       bool pll_mismatch = false;
        u8 pipe_mask;
        bool active;
 
@@ -5116,9 +5117,18 @@ verify_single_dpll_state(struct intel_display *display,
                                 "%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
                                 pll->info->name, pipe_mask, pll->state.pipe_mask);
 
-       if (INTEL_DISPLAY_STATE_WARN(display,
-                                    pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
-                                                      sizeof(dpll_hw_state)),
+       if (pll->on) {
+               const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
+
+               if (HAS_LT_PHY(display))
+                       pll_mismatch = !dpll_mgr->compare_hw_state(&pll->state.hw_state,
+                                                                  &dpll_hw_state);
+               else
+                       pll_mismatch = memcmp(&pll->state.hw_state, &dpll_hw_state,
+                                             sizeof(dpll_hw_state));
+       }
+
+       if (INTEL_DISPLAY_STATE_WARN(display, pll_mismatch,
                                     "%s: pll hw state mismatch\n",
                                     pll->info->name)) {
                struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
index dd8b99f8821ef35023e0e84adaa552fcc5598666..5bbbc618286191b0935d6e7e74ec4498bad2ab74 100644 (file)
@@ -2268,45 +2268,6 @@ bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
        return true;
 }
 
-void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
-                                  struct intel_crtc *crtc)
-{
-       struct intel_display *display = to_intel_display(state);
-       struct intel_digital_port *dig_port;
-       const struct intel_crtc_state *new_crtc_state =
-               intel_atomic_get_new_crtc_state(state, crtc);
-       struct intel_encoder *encoder;
-       struct intel_lt_phy_pll_state pll_hw_state = {};
-       const struct intel_lt_phy_pll_state *pll_sw_state = &new_crtc_state->dpll_hw_state.ltpll;
-
-       if (DISPLAY_VER(display) < 35)
-               return;
-
-       if (!new_crtc_state->hw.active)
-               return;
-
-       /* intel_get_crtc_new_encoder() only works for modeset/fastset commits */
-       if (!intel_crtc_needs_modeset(new_crtc_state) &&
-           !intel_crtc_needs_fastset(new_crtc_state))
-               return;
-
-       encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
-       intel_lt_phy_pll_readout_hw_state(encoder, &pll_hw_state);
-
-       dig_port = enc_to_dig_port(encoder);
-       if (intel_tc_port_in_tbt_alt_mode(dig_port))
-               return;
-
-       INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[0] != pll_sw_state->config[0],
-                                "[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG 0: (expected 0x%04x, found 0x%04x)",
-                                crtc->base.base.id, crtc->base.name,
-                                pll_sw_state->config[0], pll_hw_state.config[0]);
-       INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[2] != pll_sw_state->config[2],
-                                "[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG 2: (expected 0x%04x, found 0x%04x)",
-                                crtc->base.base.id, crtc->base.name,
-                                pll_sw_state->config[2], pll_hw_state.config[2]);
-}
-
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
                              struct intel_dpll *pll,
                              const struct intel_dpll_hw_state *dpll_hw_state)
index 147ae431713d66dd75de6fc53f1cd34f7cdcefaa..16de39484779b18511338d9905407c17b510183f 100644 (file)
@@ -41,8 +41,6 @@ bool intel_lt_phy_tbt_pll_readout_hw_state(struct intel_display *display,
                                           struct intel_dpll_hw_state *hw_state);
 bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
                                       struct intel_lt_phy_pll_state *pll_state);
-void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
-                                  struct intel_crtc *crtc);
 int
 intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
                                  u32 frequency_khz);
index 12a00121c274f5d1bb04e8bcfe58fb7a6f01dcef..2ec17c2bfe0fe23497b989846f2c771042542201 100644 (file)
@@ -246,7 +246,6 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state,
        verify_crtc_state(state, crtc);
        intel_dpll_state_verify(state, crtc);
        intel_mpllb_state_verify(state, crtc);
-       intel_lt_phy_pll_state_verify(state, crtc);
 }
 
 void intel_modeset_verify_disabled(struct intel_atomic_state *state)