spin_unlock_bh(&dp->tx_bank_lock);
if (configure_register)
- ath12k_wifi7_hal_tx_configure_bank_register(ab, bank_config,
- bank_id);
+ ath12k_hal_tx_configure_bank_register(ab,
+ bank_config, bank_id);
ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt tcl bank_id %d input 0x%x match 0x%x num_users %u",
bank_id, bank_config, dp->bank_profiles[bank_id].bank_config,
return;
if (dp->reoq_lut.vaddr_unaligned) {
- ath12k_hif_write32(ab,
- HAL_SEQ_WCSS_UMAC_REO_REG +
- HAL_REO1_QDESC_LUT_BASE0(dp->hal), 0);
+ ath12k_hal_write_reoq_lut_addr(ab, 0);
dma_free_coherent(ab->dev, dp->reoq_lut.size,
dp->reoq_lut.vaddr_unaligned,
dp->reoq_lut.paddr_unaligned);
}
if (dp->ml_reoq_lut.vaddr_unaligned) {
- ath12k_hif_write32(ab,
- HAL_SEQ_WCSS_UMAC_REO_REG +
- HAL_REO1_QDESC_LUT_BASE1(dp->hal), 0);
+ ath12k_hal_write_ml_reoq_lut_addr(ab, 0);
dma_free_coherent(ab->dev, dp->ml_reoq_lut.size,
dp->ml_reoq_lut.vaddr_unaligned,
dp->ml_reoq_lut.paddr_unaligned);
static int ath12k_dp_reoq_lut_setup(struct ath12k_base *ab)
{
struct ath12k_dp *dp = ath12k_ab_to_dp(ab);
- struct ath12k_hal *hal = dp->hal;
- u32 val;
int ret;
if (!ab->hw_params->reoq_lut_support)
* register only
*/
- ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE0(hal),
- dp->reoq_lut.paddr >> 8);
-
- ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE1(hal),
- dp->ml_reoq_lut.paddr >> 8);
-
- val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_ADDR(hal));
-
- ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_ADDR(hal),
- val | HAL_REO_QDESC_ADDR_READ_LUT_ENABLE);
-
- ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_MAX_PEERID(hal),
- HAL_REO_QDESC_MAX_PEERID);
+ ath12k_hal_write_reoq_lut_addr(ab, dp->reoq_lut.paddr >> 8);
+ ath12k_hal_write_ml_reoq_lut_addr(ab, dp->ml_reoq_lut.paddr >> 8);
+ ath12k_hal_reoq_lut_addr_read_enable(ab);
+ ath12k_hal_reoq_lut_set_max_peerid(ab);
return 0;
}
}
for (i = 0; i < HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX; i++)
- ath12k_wifi7_hal_tx_set_dscp_tid_map(ab, i);
+ ath12k_hal_tx_set_dscp_tid_map(ab, i);
ret = ath12k_dp_rx_alloc(ab);
if (ret)
return hal->hal_ops->ce_get_desc_size(type);
}
+void ath12k_hal_tx_set_dscp_tid_map(struct ath12k_base *ab, int id)
+{
+ ab->hal.hal_ops->tx_set_dscp_tid_map(ab, id);
+}
+
+void ath12k_hal_tx_configure_bank_register(struct ath12k_base *ab,
+ u32 bank_config, u8 bank_id)
+{
+ ab->hal.hal_ops->tx_configure_bank_register(ab, bank_config, bank_id);
+}
+
+void ath12k_hal_reoq_lut_addr_read_enable(struct ath12k_base *ab)
+{
+ ab->hal.hal_ops->reoq_lut_addr_read_enable(ab);
+}
+
+void ath12k_hal_reoq_lut_set_max_peerid(struct ath12k_base *ab)
+{
+ ab->hal.hal_ops->reoq_lut_set_max_peerid(ab);
+}
+
+void ath12k_hal_write_ml_reoq_lut_addr(struct ath12k_base *ab, dma_addr_t paddr)
+{
+ ab->hal.hal_ops->write_ml_reoq_lut_addr(ab, paddr);
+}
+
+void ath12k_hal_write_reoq_lut_addr(struct ath12k_base *ab, dma_addr_t paddr)
+{
+ ab->hal.hal_ops->write_reoq_lut_addr(ab, paddr);
+}
+
+void ath12k_hal_setup_link_idle_list(struct ath12k_base *ab,
+ struct hal_wbm_idle_scatter_list *sbuf,
+ u32 nsbufs, u32 tot_link_desc,
+ u32 end_offset)
+{
+ ab->hal.hal_ops->setup_link_idle_list(ab, sbuf, nsbufs, tot_link_desc,
+ end_offset);
+}
+
static int ath12k_hal_alloc_cont_rdp(struct ath12k_hal *hal)
{
size_t size;
srng->timestamp = jiffies;
}
-void ath12k_hal_setup_link_idle_list(struct ath12k_base *ab,
- struct hal_wbm_idle_scatter_list *sbuf,
- u32 nsbufs, u32 tot_link_desc,
- u32 end_offset)
-{
- struct ath12k_hal *hal = &ab->hal;
- struct ath12k_buffer_addr *link_addr;
- int i;
- u32 reg_scatter_buf_sz = HAL_WBM_IDLE_SCATTER_BUF_SIZE / 64;
- u32 val;
-
- link_addr = (void *)sbuf[0].vaddr + HAL_WBM_IDLE_SCATTER_BUF_SIZE;
-
- for (i = 1; i < nsbufs; i++) {
- link_addr->info0 = cpu_to_le32(sbuf[i].paddr & HAL_ADDR_LSB_REG_MASK);
-
- link_addr->info1 =
- le32_encode_bits((u64)sbuf[i].paddr >> HAL_ADDR_MSB_REG_SHIFT,
- HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32) |
- le32_encode_bits(BASE_ADDR_MATCH_TAG_VAL,
- HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG);
-
- link_addr = (void *)sbuf[i].vaddr +
- HAL_WBM_IDLE_SCATTER_BUF_SIZE;
- }
-
- val = u32_encode_bits(reg_scatter_buf_sz, HAL_WBM_SCATTER_BUFFER_SIZE) |
- u32_encode_bits(0x1, HAL_WBM_LINK_DESC_IDLE_LIST_MODE);
-
- ath12k_hif_write32(ab,
- HAL_SEQ_WCSS_UMAC_WBM_REG +
- HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR(hal),
- val);
-
- val = u32_encode_bits(reg_scatter_buf_sz * nsbufs,
- HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST);
- ath12k_hif_write32(ab,
- HAL_SEQ_WCSS_UMAC_WBM_REG +
- HAL_WBM_R0_IDLE_LIST_SIZE_ADDR(hal),
- val);
-
- val = u32_encode_bits(sbuf[0].paddr & HAL_ADDR_LSB_REG_MASK,
- BUFFER_ADDR_INFO0_ADDR);
- ath12k_hif_write32(ab,
- HAL_SEQ_WCSS_UMAC_WBM_REG +
- HAL_WBM_SCATTERED_RING_BASE_LSB(hal),
- val);
-
- val = u32_encode_bits(BASE_ADDR_MATCH_TAG_VAL,
- HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG) |
- u32_encode_bits((u64)sbuf[0].paddr >> HAL_ADDR_MSB_REG_SHIFT,
- HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32);
- ath12k_hif_write32(ab,
- HAL_SEQ_WCSS_UMAC_WBM_REG +
- HAL_WBM_SCATTERED_RING_BASE_MSB(hal),
- val);
-
- /* Setup head and tail pointers for the idle list */
- val = u32_encode_bits(sbuf[nsbufs - 1].paddr, BUFFER_ADDR_INFO0_ADDR);
- ath12k_hif_write32(ab,
- HAL_SEQ_WCSS_UMAC_WBM_REG +
- HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0(hal),
- val);
-
- val = u32_encode_bits(((u64)sbuf[nsbufs - 1].paddr >> HAL_ADDR_MSB_REG_SHIFT),
- HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32) |
- u32_encode_bits((end_offset >> 2),
- HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1);
- ath12k_hif_write32(ab,
- HAL_SEQ_WCSS_UMAC_WBM_REG +
- HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1(hal),
- val);
-
- val = u32_encode_bits(sbuf[0].paddr, BUFFER_ADDR_INFO0_ADDR);
- ath12k_hif_write32(ab,
- HAL_SEQ_WCSS_UMAC_WBM_REG +
- HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0(hal),
- val);
-
- val = u32_encode_bits(sbuf[0].paddr, BUFFER_ADDR_INFO0_ADDR);
- ath12k_hif_write32(ab,
- HAL_SEQ_WCSS_UMAC_WBM_REG +
- HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0(hal),
- val);
-
- val = u32_encode_bits(((u64)sbuf[0].paddr >> HAL_ADDR_MSB_REG_SHIFT),
- HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32) |
- u32_encode_bits(0, HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1);
- ath12k_hif_write32(ab,
- HAL_SEQ_WCSS_UMAC_WBM_REG +
- HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1(hal),
- val);
-
- val = 2 * tot_link_desc;
- ath12k_hif_write32(ab,
- HAL_SEQ_WCSS_UMAC_WBM_REG +
- HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR(hal),
- val);
-
- /* Enable the SRNG */
- val = u32_encode_bits(1, HAL_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE) |
- u32_encode_bits(1, HAL_WBM_IDLE_LINK_RING_MISC_RIND_ID_DISABLE);
- ath12k_hif_write32(ab,
- HAL_SEQ_WCSS_UMAC_WBM_REG +
- HAL_WBM_IDLE_LINK_RING_MISC_ADDR(hal),
- val);
-}
-
int ath12k_hal_srng_setup(struct ath12k_base *ab, enum hal_ring_type type,
int ring_num, int mac_id,
struct hal_srng_params *params)
void (*set_link_desc_addr)(struct hal_wbm_link_desc *desc, u32 cookie,
dma_addr_t paddr,
enum hal_rx_buf_return_buf_manager rbm);
+ void (*tx_set_dscp_tid_map)(struct ath12k_base *ab, int id);
+ void (*tx_configure_bank_register)(struct ath12k_base *ab,
+ u32 bank_config, u8 bank_id);
+ void (*reoq_lut_addr_read_enable)(struct ath12k_base *ab);
+ void (*reoq_lut_set_max_peerid)(struct ath12k_base *ab);
+ void (*write_ml_reoq_lut_addr)(struct ath12k_base *ab,
+ dma_addr_t paddr);
+ void (*write_reoq_lut_addr)(struct ath12k_base *ab, dma_addr_t paddr);
+ void (*setup_link_idle_list)(struct ath12k_base *ab,
+ struct hal_wbm_idle_scatter_list *sbuf,
+ u32 nsbufs, u32 tot_link_desc,
+ u32 end_offset);
};
u32 ath12k_wifi7_hal_reo_qdesc_size(u32 ba_window_size, u8 tid);
void ath12k_wifi7_hal_reo_init_cmd_ring(struct ath12k_base *ab,
struct hal_srng *srng);
void ath12k_wifi7_hal_reo_hw_setup(struct ath12k_base *ab, u32 ring_hash_map);
-
-void ath12k_hal_setup_link_idle_list(struct ath12k_base *ab,
- struct hal_wbm_idle_scatter_list *sbuf,
- u32 nsbufs, u32 tot_link_desc,
- u32 end_offset);
-
dma_addr_t ath12k_hal_srng_get_tp_addr(struct ath12k_base *ab,
struct hal_srng *srng);
dma_addr_t ath12k_hal_srng_get_hp_addr(struct ath12k_base *ab,
void ath12k_hal_set_link_desc_addr(struct ath12k_hal *hal,
struct hal_wbm_link_desc *desc, u32 cookie,
dma_addr_t paddr, int rbm);
+void ath12k_hal_setup_link_idle_list(struct ath12k_base *ab,
+ struct hal_wbm_idle_scatter_list *sbuf,
+ u32 nsbufs, u32 tot_link_desc,
+ u32 end_offset);
u32
ath12k_hal_ce_dst_status_get_length(struct ath12k_hal *hal,
struct hal_ce_srng_dst_status_desc *desc);
+void ath12k_hal_tx_set_dscp_tid_map(struct ath12k_base *ab, int id);
+void ath12k_hal_tx_configure_bank_register(struct ath12k_base *ab,
+ u32 bank_config, u8 bank_id);
+void ath12k_hal_reoq_lut_addr_read_enable(struct ath12k_base *ab);
+void ath12k_hal_reoq_lut_set_max_peerid(struct ath12k_base *ab);
+void ath12k_hal_write_reoq_lut_addr(struct ath12k_base *ab, dma_addr_t paddr);
+void
+ath12k_hal_write_ml_reoq_lut_addr(struct ath12k_base *ab, dma_addr_t paddr);
#endif
#include "hal_desc.h"
#include "../hal.h"
#include "hal.h"
+#include "hal_tx.h"
#include "../debug.h"
#include "../hif.h"
#include "hal_qcn9274.h"
return len;
}
+
+void
+ath12k_wifi7_hal_setup_link_idle_list(struct ath12k_base *ab,
+ struct hal_wbm_idle_scatter_list *sbuf,
+ u32 nsbufs, u32 tot_link_desc,
+ u32 end_offset)
+{
+ struct ath12k_hal *hal = &ab->hal;
+ struct ath12k_buffer_addr *link_addr;
+ int i;
+ u32 reg_scatter_buf_sz = HAL_WBM_IDLE_SCATTER_BUF_SIZE / 64;
+ u32 val;
+
+ link_addr = (void *)sbuf[0].vaddr + HAL_WBM_IDLE_SCATTER_BUF_SIZE;
+
+ for (i = 1; i < nsbufs; i++) {
+ link_addr->info0 = cpu_to_le32(sbuf[i].paddr & HAL_ADDR_LSB_REG_MASK);
+
+ link_addr->info1 =
+ le32_encode_bits((u64)sbuf[i].paddr >> HAL_ADDR_MSB_REG_SHIFT,
+ HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32) |
+ le32_encode_bits(BASE_ADDR_MATCH_TAG_VAL,
+ HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG);
+
+ link_addr = (void *)sbuf[i].vaddr +
+ HAL_WBM_IDLE_SCATTER_BUF_SIZE;
+ }
+
+ val = u32_encode_bits(reg_scatter_buf_sz, HAL_WBM_SCATTER_BUFFER_SIZE) |
+ u32_encode_bits(0x1, HAL_WBM_LINK_DESC_IDLE_LIST_MODE);
+
+ ath12k_hif_write32(ab,
+ HAL_SEQ_WCSS_UMAC_WBM_REG +
+ HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR(hal),
+ val);
+
+ val = u32_encode_bits(reg_scatter_buf_sz * nsbufs,
+ HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST);
+ ath12k_hif_write32(ab,
+ HAL_SEQ_WCSS_UMAC_WBM_REG +
+ HAL_WBM_R0_IDLE_LIST_SIZE_ADDR(hal),
+ val);
+
+ val = u32_encode_bits(sbuf[0].paddr & HAL_ADDR_LSB_REG_MASK,
+ BUFFER_ADDR_INFO0_ADDR);
+ ath12k_hif_write32(ab,
+ HAL_SEQ_WCSS_UMAC_WBM_REG +
+ HAL_WBM_SCATTERED_RING_BASE_LSB(hal),
+ val);
+
+ val = u32_encode_bits(BASE_ADDR_MATCH_TAG_VAL,
+ HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG) |
+ u32_encode_bits((u64)sbuf[0].paddr >> HAL_ADDR_MSB_REG_SHIFT,
+ HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32);
+ ath12k_hif_write32(ab,
+ HAL_SEQ_WCSS_UMAC_WBM_REG +
+ HAL_WBM_SCATTERED_RING_BASE_MSB(hal),
+ val);
+
+ /* Setup head and tail pointers for the idle list */
+ val = u32_encode_bits(sbuf[nsbufs - 1].paddr, BUFFER_ADDR_INFO0_ADDR);
+ ath12k_hif_write32(ab,
+ HAL_SEQ_WCSS_UMAC_WBM_REG +
+ HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0(hal),
+ val);
+
+ val = u32_encode_bits(((u64)sbuf[nsbufs - 1].paddr >> HAL_ADDR_MSB_REG_SHIFT),
+ HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32) |
+ u32_encode_bits((end_offset >> 2),
+ HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1);
+ ath12k_hif_write32(ab,
+ HAL_SEQ_WCSS_UMAC_WBM_REG +
+ HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1(hal),
+ val);
+
+ val = u32_encode_bits(sbuf[0].paddr, BUFFER_ADDR_INFO0_ADDR);
+ ath12k_hif_write32(ab,
+ HAL_SEQ_WCSS_UMAC_WBM_REG +
+ HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0(hal),
+ val);
+
+ val = u32_encode_bits(sbuf[0].paddr, BUFFER_ADDR_INFO0_ADDR);
+ ath12k_hif_write32(ab,
+ HAL_SEQ_WCSS_UMAC_WBM_REG +
+ HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0(hal),
+ val);
+
+ val = u32_encode_bits(((u64)sbuf[0].paddr >> HAL_ADDR_MSB_REG_SHIFT),
+ HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32) |
+ u32_encode_bits(0, HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1);
+ ath12k_hif_write32(ab,
+ HAL_SEQ_WCSS_UMAC_WBM_REG +
+ HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1(hal),
+ val);
+
+ val = 2 * tot_link_desc;
+ ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_WBM_REG +
+ HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR(hal),
+ val);
+
+ /* Enable the SRNG */
+ val = u32_encode_bits(1, HAL_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE) |
+ u32_encode_bits(1, HAL_WBM_IDLE_LINK_RING_MISC_RIND_ID_DISABLE);
+ ath12k_hif_write32(ab,
+ HAL_SEQ_WCSS_UMAC_WBM_REG +
+ HAL_WBM_IDLE_LINK_RING_MISC_ADDR(hal),
+ val);
+}
+
+void ath12k_wifi7_hal_tx_configure_bank_register(struct ath12k_base *ab,
+ u32 bank_config,
+ u8 bank_id)
+{
+ ath12k_hif_write32(ab, HAL_TCL_SW_CONFIG_BANK_ADDR + 4 * bank_id,
+ bank_config);
+}
+
+void ath12k_wifi7_hal_reoq_lut_addr_read_enable(struct ath12k_base *ab)
+{
+ struct ath12k_hal *hal = &ab->hal;
+
+ u32 val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_REO_REG +
+ HAL_REO1_QDESC_ADDR(hal));
+
+ ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_ADDR(hal),
+ val | HAL_REO_QDESC_ADDR_READ_LUT_ENABLE);
+}
+
+void ath12k_wifi7_hal_reoq_lut_set_max_peerid(struct ath12k_base *ab)
+{
+ struct ath12k_hal *hal = &ab->hal;
+
+ ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_MAX_PEERID(hal),
+ HAL_REO_QDESC_MAX_PEERID);
+}
+
+void ath12k_wifi7_hal_write_reoq_lut_addr(struct ath12k_base *ab,
+ dma_addr_t paddr)
+{
+ ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG +
+ HAL_REO1_QDESC_LUT_BASE0(&ab->hal), paddr);
+}
+
+void ath12k_wifi7_hal_write_ml_reoq_lut_addr(struct ath12k_base *ab,
+ dma_addr_t paddr)
+{
+ ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG +
+ HAL_REO1_QDESC_LUT_BASE1(&ab->hal), paddr);
+}
enum hal_rx_buf_return_buf_manager rbm);
u32
ath12k_wifi7_hal_ce_dst_status_get_length(struct hal_ce_srng_dst_status_desc *desc);
+void
+ath12k_wifi7_hal_setup_link_idle_list(struct ath12k_base *ab,
+ struct hal_wbm_idle_scatter_list *sbuf,
+ u32 nsbufs, u32 tot_link_desc,
+ u32 end_offset);
+void ath12k_wifi7_hal_reoq_lut_addr_read_enable(struct ath12k_base *ab);
+void ath12k_wifi7_hal_reoq_lut_set_max_peerid(struct ath12k_base *ab);
+void ath12k_wifi7_hal_write_reoq_lut_addr(struct ath12k_base *ab,
+ dma_addr_t paddr);
+void ath12k_wifi7_hal_write_ml_reoq_lut_addr(struct ath12k_base *ab,
+ dma_addr_t paddr);
#endif
#include "hal_qcn9274.h"
#include "hw.h"
#include "hal.h"
+#include "hal_tx.h"
static const struct hal_srng_config hw_srng_config_template[] = {
/* TODO: max_rings can populated by querying HW capabilities */
.ce_dst_set_desc = ath12k_wifi7_hal_ce_dst_set_desc,
.ce_dst_status_get_length = ath12k_wifi7_hal_ce_dst_status_get_length,
.set_link_desc_addr = ath12k_wifi7_hal_set_link_desc_addr,
+ .tx_set_dscp_tid_map = ath12k_wifi7_hal_tx_set_dscp_tid_map,
+ .tx_configure_bank_register =
+ ath12k_wifi7_hal_tx_configure_bank_register,
+ .reoq_lut_addr_read_enable = ath12k_wifi7_hal_reoq_lut_addr_read_enable,
+ .reoq_lut_set_max_peerid = ath12k_wifi7_hal_reoq_lut_set_max_peerid,
+ .write_reoq_lut_addr = ath12k_wifi7_hal_write_reoq_lut_addr,
+ .write_ml_reoq_lut_addr = ath12k_wifi7_hal_write_ml_reoq_lut_addr,
+ .setup_link_idle_list = ath12k_wifi7_hal_setup_link_idle_list,
};
EXPORT_SYMBOL(hal_qcn9274_ops);
HAL_TCL1_RING_CMN_CTRL_REG,
ctrl_reg_val);
}
-
-void ath12k_wifi7_hal_tx_configure_bank_register(struct ath12k_base *ab,
- u32 bank_config,
- u8 bank_id)
-{
- ath12k_hif_write32(ab, HAL_TCL_SW_CONFIG_BANK_ADDR + 4 * bank_id,
- bank_config);
-}
/* STA mode will have MCAST_PKT_CTRL instead of DSCP_TID_MAP bitfield */
#define HAL_TX_BANK_CONFIG_DSCP_TIP_MAP_ID GENMASK(22, 17)
+void ath12k_wifi7_hal_tx_set_dscp_tid_map(struct ath12k_base *ab, int id);
void ath12k_wifi7_hal_tx_cmd_desc_setup(struct ath12k_base *ab,
struct hal_tcl_data_cmd *tcl_cmd,
struct hal_tx_info *ti);
-void ath12k_wifi7_hal_tx_set_dscp_tid_map(struct ath12k_base *ab, int id);
int ath12k_wifi7_hal_reo_cmd_send(struct ath12k_base *ab, struct hal_srng *srng,
enum hal_reo_cmd_type type,
struct ath12k_hal_reo_cmd *cmd);
void ath12k_wifi7_hal_tx_configure_bank_register(struct ath12k_base *ab,
- u32 bank_config, u8 bank_id);
+ u32 bank_config,
+ u8 bank_id);
#endif
#include "hal_wcn7850.h"
#include "hw.h"
#include "hal.h"
+#include "hal_tx.h"
static const struct hal_srng_config hw_srng_config_template[] = {
/* TODO: max_rings can populated by querying HW capabilities */
.ce_dst_set_desc = ath12k_wifi7_hal_ce_dst_set_desc,
.ce_dst_status_get_length = ath12k_wifi7_hal_ce_dst_status_get_length,
.set_link_desc_addr = ath12k_wifi7_hal_set_link_desc_addr,
+ .tx_set_dscp_tid_map = ath12k_wifi7_hal_tx_set_dscp_tid_map,
+ .tx_configure_bank_register =
+ ath12k_wifi7_hal_tx_configure_bank_register,
+ .reoq_lut_addr_read_enable = ath12k_wifi7_hal_reoq_lut_addr_read_enable,
+ .reoq_lut_set_max_peerid = ath12k_wifi7_hal_reoq_lut_set_max_peerid,
+ .write_reoq_lut_addr = ath12k_wifi7_hal_write_reoq_lut_addr,
+ .write_ml_reoq_lut_addr = ath12k_wifi7_hal_write_ml_reoq_lut_addr,
+ .setup_link_idle_list = ath12k_wifi7_hal_setup_link_idle_list,
};
EXPORT_SYMBOL(hal_wcn7850_ops);
projects / thirdparty / kernel / linux.git / commitdiff
