Fix misdetected Slow_SSE4_2 cpu feature bit (bug 17501)

diff --git a/ChangeLog b/ChangeLog
index 149ecc41ce35ce5e3fcf0707d7b1e6301e7dcbde..f97b361d24deeea83d67ade7640c8f50d55c0f16 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,13 @@
+2014-10-27  Andreas Schwab  <schwab@suse.de>
+
+       [BZ #17501]
+       * sysdeps/i386/i686/multiarch/strcasecmp.S (__strcasecmp): Fix
+       check for Slow_SSE4_2 feature bit.
+       * sysdeps/i386/i686/multiarch/strcmp.S (STRCMP): Likewise.
+       * sysdeps/i386/i686/multiarch/strncase.S (__strncasecmp): Likewise.
+       * sysdeps/x86_64/multiarch/strcmp.S (STRCMP, __strcascmp):
+       Likewise.  Fix check for Fast_Unaligned_Load feature bit.
+
 2014-10-24  Roland McGrath  <roland@hack.frob.com>
 
        * configure.ac: Validate compiler version with a empirical test of

diff --git a/NEWS b/NEWS
index 13be62e8c706f731060252c52eb1604a0db4a7f7..d08117e8b2cfa6a0a25204c1c6e1d211984a2b60 100644 (file)
--- a/NEWS
+++ b/NEWS
@@ -10,7 +10,7 @@ Version 2.21
 * The following bugs are resolved with this release:
 
   6652, 12926, 14171, 15884, 17266, 17363, 17370, 17371, 17411, 17460,
-  17485, 17508.
+  17485, 17501, 17508.
 \f
 Version 2.20
 

diff --git a/sysdeps/i386/i686/multiarch/strcasecmp.S b/sysdeps/i386/i686/multiarch/strcasecmp.S
index 4f2de4f37b16a791c4e50dfdc42a895e42f220b4..57ccef51a0788812ab5279f5130bc6d374c75fe6 100644 (file)
--- a/sysdeps/i386/i686/multiarch/strcasecmp.S
+++ b/sysdeps/i386/i686/multiarch/strcasecmp.S
@@ -37,7 +37,7 @@ ENTRY(__strcasecmp)
        leal    __strcasecmp_ssse3@GOTOFF(%ebx), %eax
        testl   $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
        jz      2f
-       testl   $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
+       testl   $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
        jnz     2f
        leal    __strcasecmp_sse4_2@GOTOFF(%ebx), %eax
 2:     popl    %ebx
@@ -58,7 +58,7 @@ ENTRY(__strcasecmp)
        leal    __strcasecmp_ssse3, %eax
        testl   $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
        jz      2f
-       testl   $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features
+       testl   $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features
        jnz     2f
        leal    __strcasecmp_sse4_2, %eax
 2:     ret

diff --git a/sysdeps/i386/i686/multiarch/strcmp.S b/sysdeps/i386/i686/multiarch/strcmp.S
index 2ad6bf4212cf391489f11a70fc7d17fb47815ca6..23cbd6f3c572fbcb160d930504ad303351f18fba 100644 (file)
--- a/sysdeps/i386/i686/multiarch/strcmp.S
+++ b/sysdeps/i386/i686/multiarch/strcmp.S
@@ -68,7 +68,7 @@ ENTRY(STRCMP)
        leal    __STRCMP_SSSE3@GOTOFF(%ebx), %eax
        testl   $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
        jz      2f
-       testl   $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
+       testl   $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
        jnz     2f
        leal    __STRCMP_SSE4_2@GOTOFF(%ebx), %eax
 2:     popl    %ebx
@@ -89,7 +89,7 @@ ENTRY(STRCMP)
        leal    __STRCMP_SSSE3, %eax
        testl   $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
        jz      2f
-       testl   $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features
+       testl   $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features
        jnz     2f
        leal    __STRCMP_SSE4_2, %eax
 2:     ret

diff --git a/sysdeps/i386/i686/multiarch/strncase.S b/sysdeps/i386/i686/multiarch/strncase.S
index 9b4cfa063a6612f5de53a17fea2fc0b4fb1570de..41644a58767d297eda78b4ac13b29225253ae798 100644 (file)
--- a/sysdeps/i386/i686/multiarch/strncase.S
+++ b/sysdeps/i386/i686/multiarch/strncase.S
@@ -37,7 +37,7 @@ ENTRY(__strncasecmp)
        leal    __strncasecmp_ssse3@GOTOFF(%ebx), %eax
        testl   $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
        jz      2f
-       testl   $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
+       testl   $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
        jnz     2f
        leal    __strncasecmp_sse4_2@GOTOFF(%ebx), %eax
 2:     popl    %ebx
@@ -58,7 +58,7 @@ ENTRY(__strncasecmp)
        leal    __strncasecmp_ssse3, %eax
        testl   $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
        jz      2f
-       testl   $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features
+       testl   $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features
        jnz     2f
        leal    __strncasecmp_sse4_2, %eax
 2:     ret

diff --git a/sysdeps/x86_64/multiarch/strcmp.S b/sysdeps/x86_64/multiarch/strcmp.S
index f3e0ca1259f28aaba2ab6e46fd310d3a9413d38d..bd71714e0b8c5290f9c15aeb4478a4bb6c125092 100644 (file)
--- a/sysdeps/x86_64/multiarch/strcmp.S
+++ b/sysdeps/x86_64/multiarch/strcmp.S
@@ -91,10 +91,10 @@ ENTRY(STRCMP)
 1:
 #ifdef USE_AS_STRCMP
        leaq    __strcmp_sse2_unaligned(%rip), %rax
-       testl   $bit_Fast_Unaligned_Load, __cpu_features+CPUID_OFFSET+index_Fast_Unaligned_Load(%rip)
+       testl   $bit_Fast_Unaligned_Load, __cpu_features+FEATURE_OFFSET+index_Fast_Unaligned_Load(%rip)
        jnz     3f
 #else
-       testl   $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip)
+       testl   $bit_Slow_SSE4_2, __cpu_features+FEATURE_OFFSET+index_Slow_SSE4_2(%rip)
        jnz     2f
        leaq    STRCMP_SSE42(%rip), %rax
        testl   $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
@@ -120,7 +120,7 @@ ENTRY(__strcasecmp)
        testl   $bit_AVX_Usable, __cpu_features+FEATURE_OFFSET+index_AVX_Usable(%rip)
        jnz     3f
 #  endif
-       testl   $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip)
+       testl   $bit_Slow_SSE4_2, __cpu_features+FEATURE_OFFSET+index_Slow_SSE4_2(%rip)
        jnz     2f
        leaq    __strcasecmp_sse42(%rip), %rax
        testl   $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
@@ -146,7 +146,7 @@ ENTRY(__strncasecmp)
        testl   $bit_AVX_Usable, __cpu_features+FEATURE_OFFSET+index_AVX_Usable(%rip)
        jnz     3f
 #  endif
-       testl   $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip)
+       testl   $bit_Slow_SSE4_2, __cpu_features+FEATURE_OFFSET+index_Slow_SSE4_2(%rip)
        jnz     2f
        leaq    __strncasecmp_sse42(%rip), %rax
        testl   $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)