dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controller

Add DT bindings for the Graphics clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-6-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/qcom,qcs615-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcs615-gpucc.yaml
new file mode 100644 (file)
index 0000000..5f7d83d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,qcs615-gpucc.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Graphics Clock & Reset Controller on QCS615
+
+maintainers:
+  - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+  Qualcomm graphics clock control module provides clocks, resets and power
+  domains on QCS615 Qualcomm SoCs.
+
+  See also: include/dt-bindings/clock/qcom,qcs615-gpucc.h
+
+properties:
+  compatible:
+    const: qcom,qcs615-gpucc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: GPLL0 main branch source
+      - description: GPLL0 GPUCC div branch source
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/clock/qcom,qcs615-gcc.h>
+
+    clock-controller@5090000 {
+      compatible = "qcom,qcs615-gpucc";
+      reg = <0x5090000 0x9000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&gcc GPLL0>,
+               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...

diff --git a/include/dt-bindings/clock/qcom,qcs615-gpucc.h b/include/dt-bindings/clock/qcom,qcs615-gpucc.h
new file mode 100644 (file)
index 0000000..6d8394b
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,qcs615-gpucc.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_QCS615_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_QCS615_H
+
+/* GPU_CC clocks */
+#define CRC_DIV_PLL0                                           0
+#define CRC_DIV_PLL1                                           1
+#define GPU_CC_PLL0                                            2
+#define GPU_CC_PLL1                                            3
+#define GPU_CC_CRC_AHB_CLK                                     4
+#define GPU_CC_CX_GFX3D_CLK                                    5
+#define GPU_CC_CX_GFX3D_SLV_CLK                                        6
+#define GPU_CC_CX_GMU_CLK                                      7
+#define GPU_CC_CX_SNOC_DVM_CLK                                 8
+#define GPU_CC_CXO_AON_CLK                                     9
+#define GPU_CC_CXO_CLK                                         10
+#define GPU_CC_GMU_CLK_SRC                                     11
+#define GPU_CC_GX_GFX3D_CLK                                    12
+#define GPU_CC_GX_GFX3D_CLK_SRC                                        13
+#define GPU_CC_GX_GMU_CLK                                      14
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK                         15
+#define GPU_CC_SLEEP_CLK                                       16
+
+/* GPU_CC power domains */
+#define CX_GDSC                                                        0
+#define GX_GDSC                                                        1
+
+/* GPU_CC resets */
+#define GPU_CC_CX_BCR                                          0
+#define GPU_CC_GFX3D_AON_BCR                                   1
+#define GPU_CC_GMU_BCR                                         2
+#define GPU_CC_GX_BCR                                          3
+#define GPU_CC_XO_BCR                                          4
+
+#endif