}
}
+static void tegra_mc_setup_intmask(struct tegra_mc *mc)
+{
+ unsigned int i;
+
+ for (i = 0; i < mc->soc->num_intmasks; i++) {
+ if (mc->soc->num_channels)
+ mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask,
+ mc->soc->intmasks[i].reg);
+ else
+ mc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg);
+ }
+}
+
static int tegra_mc_probe(struct platform_device *pdev)
{
struct tegra_mc *mc;
}
}
- for (i = 0; i < mc->soc->num_intmasks; i++) {
- if (mc->soc->num_channels)
- mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask,
- mc->soc->intmasks[i].reg);
- else
- mc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg);
- }
+ tegra_mc_setup_intmask(mc);
}
if (mc->soc->reset_ops) {
if (mc->soc->ops && mc->soc->ops->resume)
mc->soc->ops->resume(mc);
+ tegra_mc_setup_intmask(mc);
+
return 0;
}