In order to handle FPU instructions with data size of 28 and 108 bytes,

implemented a hack:  such instructions have their data_size reduced to 16
bytes for cache simulation purposes, to avoid assertion failures coming from
transfers that involve more than two cache lines.  Should occur rarely in
practice.

git-svn-id: svn://svn.valgrind.org/valgrind/branches/VALGRIND_1_0_BRANCH@861

diff --git a/vg_cachesim.c b/vg_cachesim.c
index ec5686d1da2b0b44be2a8a57fcfd36c9357f6160..ea9cbce05f183a228ef26b2732ccf128af28ab5e 100644 (file)
--- a/vg_cachesim.c
+++ b/vg_cachesim.c
@@ -40,6 +40,8 @@
 /* According to IA-32 Intel Architecture Software Developer's Manual: Vol 2 */
 #define MAX_x86_INSTR_SIZE              16
 
+#define MIN_LINE_SIZE   16
+
 /* Size of various buffers used for storing strings */
 #define FILENAME_LEN                    256
 #define FN_NAME_LEN                     256
@@ -677,7 +679,8 @@ UCodeBlock* VG_(cachesim_instrument)(UCodeBlock* cb_in, Addr orig_addr)
 
             } else { 
                vg_assert(4 == data_size || 2  == data_size || 1 == data_size || 
-                         8 == data_size || 10 == data_size);
+                         8 == data_size || 10 == data_size || 
+                         MIN_LINE_SIZE == data_size);
                
                if (IS_(read) && !IS_(write)) {
                   CC_size = sizeof(idCC);
@@ -840,7 +843,9 @@ UCodeBlock* VG_(cachesim_instrument)(UCodeBlock* cb_in, Addr orig_addr)
             t_read      = u_in->val2;
             t_read_addr = newTemp(cb);
             uInstr2(cb, MOV, 4, TempReg, u_in->val2,  TempReg, t_read_addr);
-            data_size = u_in->size;
+            data_size = ( u_in->size <= MIN_LINE_SIZE 
+                        ? u_in->size 
+                        : MIN_LINE_SIZE);
             VG_(copyUInstr)(cb, u_in);
             break;
 
@@ -854,7 +859,12 @@ UCodeBlock* VG_(cachesim_instrument)(UCodeBlock* cb_in, Addr orig_addr)
             t_write      = u_in->val2;
             t_write_addr = newTemp(cb);
             uInstr2(cb, MOV, 4, TempReg, u_in->val2, TempReg, t_write_addr);
-            data_size = u_in->size;
+            /* 28 and 108 B data-sized instructions will be done
+             * inaccurately but they're very rare and this avoids errors
+             * from hitting more than two cache lines in the simulation. */
+            data_size = ( u_in->size <= MIN_LINE_SIZE 
+                        ? u_in->size 
+                        : MIN_LINE_SIZE);
             VG_(copyUInstr)(cb, u_in);
             break;
 
@@ -878,8 +888,6 @@ UCodeBlock* VG_(cachesim_instrument)(UCodeBlock* cb_in, Addr orig_addr)
 /*--- Cache simulation stuff                               ---*/
 /*------------------------------------------------------------*/
 
-#define MIN_LINE_SIZE   16
-
 /* Total reads/writes/misses.  Calculated during CC traversal at the end. */
 static CC Ir_total;
 static CC Dr_total;