x86/msr: Switch wrmsr_on_cpu() users to wrmsrq_on_cpu()

In order to prepare retiring wrmsr_on_cpu() switch wrmsr_on_cpu() users
to wrmsrq_on_cpu().

Tested-by: K Prateek Nayak <kprateek.nayak@amd.com>
Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Rafael J. Wysocki <rafael@kernel.org>
Cc: Daniel Lezcano <daniel.lezcano@kernel.org>
Link: https://patch.msgid.link/20260608051741.3207435-6-jgross@suse.com

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 7f0d515c07c54f7bf1e04fdb058869791026f99c..5b9c01383f496df3c9d87cb06fbc4738227b9dfa 100644 (file)
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -780,9 +780,7 @@ void init_debug_store_on_cpu(int cpu)
        if (!ds)
                return;
 
-       wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
-                    (u32)((u64)(unsigned long)ds),
-                    (u32)((u64)(unsigned long)ds >> 32));
+       wrmsrq_on_cpu(cpu, MSR_IA32_DS_AREA, (u64)(unsigned long)ds);
 }
 
 void fini_debug_store_on_cpu(int cpu)
@@ -790,7 +788,7 @@ void fini_debug_store_on_cpu(int cpu)
        if (!per_cpu(cpu_hw_events, cpu).ds)
                return;
 
-       wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
+       wrmsrq_on_cpu(cpu, MSR_IA32_DS_AREA, 0);
 }
 
 static DEFINE_PER_CPU(void *, insn_buffer);
@@ -1095,8 +1093,7 @@ void init_arch_pebs_on_cpu(int cpu)
         * contiguous physical buffer (__alloc_pages_node() with order)
         */
        arch_pebs_base = virt_to_phys(cpuc->pebs_vaddr) | PEBS_BUFFER_SHIFT;
-       wrmsr_on_cpu(cpu, MSR_IA32_PEBS_BASE, (u32)arch_pebs_base,
-                    (u32)(arch_pebs_base >> 32));
+       wrmsrq_on_cpu(cpu, MSR_IA32_PEBS_BASE, arch_pebs_base);
        x86_pmu.pebs_active = 1;
 }
 
@@ -1105,7 +1102,7 @@ inline void fini_arch_pebs_on_cpu(int cpu)
        if (!x86_pmu.arch_pebs)
                return;
 
-       wrmsr_on_cpu(cpu, MSR_IA32_PEBS_BASE, 0, 0);
+       wrmsrq_on_cpu(cpu, MSR_IA32_PEBS_BASE, 0);
 }
 
 /*

diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 22f914f7affecdb3f740d94641f2f691d8b5babc..6e0d7a6335ff8f2caed537cd58bf4433fa2e4875 100644 (file)
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -291,7 +291,7 @@ static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no,
 static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no,
                                struct msr __percpu *msrs)
 {
-       wrmsr_on_cpu(0, msr_no, raw_cpu_read(msrs->l), raw_cpu_read(msrs->h));
+       wrmsrq_on_cpu(0, msr_no, raw_cpu_read(msrs->q));
 }
 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
                                    u32 *l, u32 *h)

diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c
index bee9c35762b8139130a29fc87d47178a0743b50e..6d30e7720f31eef902e64be0ac167e25cf5e43c4 100644 (file)
--- a/arch/x86/kernel/cpu/mce/inject.c
+++ b/arch/x86/kernel/cpu/mce/inject.c
@@ -327,7 +327,7 @@ static int toggle_hw_mce_inject(unsigned int cpu, bool enable)
 
        enable ? (val.l |= BIT(18)) : (val.l &= ~BIT(18));
 
-       err = wrmsr_on_cpu(cpu, MSR_K7_HWCR, val.l, val.h);
+       err = wrmsrq_on_cpu(cpu, MSR_K7_HWCR, val.q);
        if (err)
                pr_err("%s: error writing HWCR\n", __func__);
 

diff --git a/drivers/cpufreq/p4-clockmod.c b/drivers/cpufreq/p4-clockmod.c
index d96e8b665f39c7baa4b14bcd9dd2a83ec03c9fa9..c1690aa481934294c674e509d3028404a2ece56a 100644 (file)
--- a/drivers/cpufreq/p4-clockmod.c
+++ b/drivers/cpufreq/p4-clockmod.c
@@ -68,7 +68,7 @@ static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate)
        rdmsrq_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &val.q);
        if (newstate == DC_DISABLE) {
                pr_debug("CPU#%d disabling modulation\n", cpu);
-               wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.l & ~(1<<4), val.h);
+               wrmsrq_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.q & ~(1ULL << 4));
        } else {
                pr_debug("CPU#%d setting duty cycle to %d%%\n",
                        cpu, ((125 * newstate) / 10));
@@ -79,7 +79,7 @@ static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate)
                 */
                val.l = (val.l & ~14);
                val.l = val.l | (1<<4) | ((newstate & 0x7)<<1);
-               wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.l, val.h);
+               wrmsrq_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.q);
        }
 
        return 0;

diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedstep-centrino.c
index cefee19d1100fc0535279dc58a5eae001b644eb4..9237ed8f2b1facfc4b3746aab5dc4af94dcb3176 100644 (file)
--- a/drivers/cpufreq/speedstep-centrino.c
+++ b/drivers/cpufreq/speedstep-centrino.c
@@ -475,7 +475,7 @@ static int centrino_target(struct cpufreq_policy *policy, unsigned int index)
                        oldmsr.l |= msr;
                }
 
-               wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr.l, oldmsr.h);
+               wrmsrq_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr.q);
                if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
                        break;
 
@@ -491,7 +491,7 @@ static int centrino_target(struct cpufreq_policy *policy, unsigned int index)
                 */
 
                for_each_cpu(j, covered_cpus)
-                       wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr.l, oldmsr.h);
+                       wrmsrq_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr.q);
        }
        retval = 0;
 

diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal/intel/x86_pkg_temp_thermal.c
index 2e7de8cf756dd0104512724c7fd155f05a4f63a2..144603c356a06eff59fe64e3928813b816a92349 100644 (file)
--- a/drivers/thermal/intel/x86_pkg_temp_thermal.c
+++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c
@@ -167,7 +167,7 @@ sys_set_trip_temp(struct thermal_zone_device *tzd,
                v.l |= intr;
        }
 
-       return wrmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, v.l, v.h);
+       return wrmsrq_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, v.q);
 }
 
 /* Thermal zone callback registry */