dt-bindings: clock, reset: Add econet EN751221

Add clock and reset bindings for EN751221 as well as a "chip-scu" which is
an additional regmap that is used by the clock driver as well as others.
This split of the SCU across two register areas is the same as the Airoha
AN758x family.

Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
index a8471367175b14feb46dd9f1539a2000ca33b7fd..eb24a5687639e064752faab71305d7bbcba7bd1f 100644 (file)
--- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
+++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
@@ -32,6 +32,7 @@ properties:
       - enum:
           - airoha,en7523-scu
           - airoha,en7581-scu
+          - econet,en751221-scu
 
   reg:
     items:
@@ -67,7 +68,9 @@ allOf:
   - if:
       properties:
         compatible:
-          const: airoha,en7581-scu
+          enum:
+            - airoha,en7581-scu
+            - econet,en751221-scu
     then:
       properties:
         reg:
@@ -98,3 +101,4 @@ examples:
               #reset-cells = <1>;
       };
     };
+

diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index e57add2bacd30b0582e037ae69dd9f2b55d13066..e228670880631429836b542ea5d40100b73d69e1 100644 (file)
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -61,6 +61,7 @@ select:
           - cirrus,ep7209-syscon2
           - cirrus,ep7209-syscon3
           - cnxt,cx92755-uc
+          - econet,en751221-chip-scu
           - freecom,fsg-cs2-system-controller
           - fsl,imx93-aonmix-ns-syscfg
           - fsl,imx93-wakeupmix-syscfg
@@ -173,6 +174,7 @@ properties:
               - cirrus,ep7209-syscon2
               - cirrus,ep7209-syscon3
               - cnxt,cx92755-uc
+              - econet,en751221-chip-scu
               - freecom,fsg-cs2-system-controller
               - fsl,imx93-aonmix-ns-syscfg
               - fsl,imx93-wakeupmix-syscfg

diff --git a/MAINTAINERS b/MAINTAINERS
index 7d10988cbc62b77515aa1a1fee1c7d3e594869fa..8895a43d68de8c32f29d4771ccc0ff29f4acbf4d 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9096,6 +9096,8 @@ F:        arch/mips/boot/dts/econet/
 F:     arch/mips/econet/
 F:     drivers/clocksource/timer-econet-en751221.c
 F:     drivers/irqchip/irq-econet-en751221.c
+F:     include/dt-bindings/clock/econet,en751221-scu.h
+F:     include/dt-bindings/reset/econet,en751221-scu.h
 
 ECRYPT FILE SYSTEM
 M:     Tyler Hicks <code@tyhicks.com>

diff --git a/include/dt-bindings/clock/econet,en751221-scu.h b/include/dt-bindings/clock/econet,en751221-scu.h
new file mode 100644 (file)
index 0000000..318ec8a
--- /dev/null
+++ b/include/dt-bindings/clock/econet,en751221-scu.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_
+#define _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_
+
+#define EN751221_CLK_PCIE      0
+#define EN751221_CLK_SPI       1
+#define EN751221_CLK_BUS       2
+#define EN751221_CLK_CPU       3
+#define EN751221_CLK_GSW       4
+
+#endif /* _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_ */

diff --git a/include/dt-bindings/reset/econet,en751221-scu.h b/include/dt-bindings/reset/econet,en751221-scu.h
new file mode 100644 (file)
index 0000000..bad499d
--- /dev/null
+++ b/include/dt-bindings/reset/econet,en751221-scu.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_
+#define __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_
+
+#define EN751221_XPON_PHY_RST           0
+#define EN751221_PCM1_ZSI_ISI_RST       1
+#define EN751221_FE_QDMA1_RST           2
+#define EN751221_FE_QDMA2_RST           3
+#define EN751221_FE_UNZIP_RST           4
+#define EN751221_PCM2_RST               5
+#define EN751221_PTM_MAC_RST            6
+#define EN751221_CRYPTO_RST             7
+#define EN751221_SAR_RST                8
+#define EN751221_TIMER_RST              9
+#define EN751221_INTC_RST              10
+#define EN751221_BONDING_RST           11
+#define EN751221_PCM1_RST              12
+#define EN751221_UART_RST              13
+#define EN751221_GPIO_RST              14
+#define EN751221_GDMA_RST              15
+#define EN751221_I2C_MASTER_RST                16
+#define EN751221_PCM2_ZSI_ISI_RST      17
+#define EN751221_SFC_RST               18
+#define EN751221_UART2_RST             19
+#define EN751221_GDMP_RST              20
+#define EN751221_FE_RST                        21
+#define EN751221_USB_HOST_P0_RST       22
+#define EN751221_GSW_RST               23
+#define EN751221_SFC2_PCM_RST          24
+#define EN751221_PCIE0_RST             25
+#define EN751221_PCIE1_RST             26
+#define EN751221_CPU_TIMER_RST         27
+#define EN751221_PCIE_HB_RST           28
+#define EN751221_SIMIF_RST             29
+#define EN751221_XPON_MAC_RST          30
+#define EN751221_GFAST_RST             31
+#define EN751221_CPU_TIMER2_RST                32
+#define EN751221_UART3_RST             33
+#define EN751221_UART4_RST             34
+#define EN751221_UART5_RST             35
+#define EN751221_I2C2_RST              36
+#define EN751221_XSI_MAC_RST           37
+#define EN751221_XSI_PHY_RST           38
+#define EN751221_DMT_RST               39
+#define EN751221_USB_PHY_P0_RST                40
+#define EN751221_USB_PHY_P1_RST                41
+
+#endif /* __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_ */