aarch64: Extend iterator support for partial SVE FP modes

Define new iterators for partial floating-point modes, and cover these
in some existing mode_attrs.  This patch serves as a starting point for
an effort to extend support for unpacked floating-point operations.

To differentiate between BFloat mode iterators that need to test
TARGET_SSVE_B16B16, and those that don't (see LOGICALF), this patch
enforces the following naming convention:
	- _BF: BF16 modes will not test TARGET_SSVE_B16B16.
	- _B16B16: BF16 modes will test TARGET_SSVE_B16B16.

gcc/ChangeLog:

	* config/aarch64/aarch64-sve.md: Replace uses of SVE_FULL_F_BF
	with SVE_FULL_F_B16B16.
	Replace use of SVE_F with SVE_F_BF.
	* config/aarch64/iterators.md (SVE_PARTIAL_F): New iterator for
	partial SVE FP modes.
	(SVE_FULL_F_BF): Rename to SVE_FULL_F_B16B16.
	(SVE_PARTIAL_F_B16B16): New iterator (BF16 included) for partial
	SVE FP modes.
	(SVE_F_B16B16): New iterator for all SVE FP modes.
	(SVE_BF): New iterator for all SVE BF16 modes.
	(SVE_F): Redefine to exclude BF16 modes.
	(SVE_F_BF): New iterator to replace the previous SVE_F.
	(VPRED): Describe the VPRED mapping for partial vector modes.
	(b): Cover partial FP modes.
	(is_bf16): Likewise.

diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 7cb13e73d0d473d0a2394703ab82ebd977e66e08..180c6dd9e5b5873a4ba0e32064df64ccd3dbff1f 100644 (file)
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -5493,27 +5493,27 @@
 ;; Split a predicated instruction whose predicate is unused into an
 ;; unpredicated instruction.
 (define_split
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand")
-       (unspec:SVE_FULL_F_BF
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand")
+       (unspec:SVE_FULL_F_B16B16
          [(match_operand:<VPRED> 1 "register_operand")
           (match_operand:SI 4 "aarch64_sve_gp_strictness")
-          (match_operand:SVE_FULL_F_BF 2 "register_operand")
-          (match_operand:SVE_FULL_F_BF 3 "register_operand")]
+          (match_operand:SVE_FULL_F_B16B16 2 "register_operand")
+          (match_operand:SVE_FULL_F_B16B16 3 "register_operand")]
          <SVE_COND_FP>))]
   "TARGET_SVE
    && reload_completed
    && INTVAL (operands[4]) == SVE_RELAXED_GP"
   [(set (match_dup 0)
-       (SVE_UNPRED_FP_BINARY:SVE_FULL_F_BF (match_dup 2) (match_dup 3)))]
+       (SVE_UNPRED_FP_BINARY:SVE_FULL_F_B16B16 (match_dup 2) (match_dup 3)))]
 )
 
 ;; Unpredicated floating-point binary operations (post-RA only).
 ;; These are generated by the split above.
 (define_insn "*post_ra_<sve_fp_op><mode>3"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand" "=w")
-       (SVE_UNPRED_FP_BINARY:SVE_FULL_F_BF
-         (match_operand:SVE_FULL_F_BF 1 "register_operand" "w")
-         (match_operand:SVE_FULL_F_BF 2 "register_operand" "w")))]
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand" "=w")
+       (SVE_UNPRED_FP_BINARY:SVE_FULL_F_B16B16
+         (match_operand:SVE_FULL_F_B16B16 1 "register_operand" "w")
+         (match_operand:SVE_FULL_F_B16B16 2 "register_operand" "w")))]
   "TARGET_SVE && reload_completed"
   "<b><sve_fp_op>\t%0.<Vetype>, %1.<Vetype>, %2.<Vetype>")
 
@@ -5557,12 +5557,12 @@
 ;; Unpredicated floating-point binary operations that need to be predicated
 ;; for SVE.
 (define_expand "<optab><mode>3"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand")
-       (unspec:SVE_FULL_F_BF
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand")
+       (unspec:SVE_FULL_F_B16B16
          [(match_dup 3)
           (const_int SVE_RELAXED_GP)
-          (match_operand:SVE_FULL_F_BF 1 "<sve_pred_fp_rhs1_operand>")
-          (match_operand:SVE_FULL_F_BF 2 "<sve_pred_fp_rhs2_operand>")]
+          (match_operand:SVE_FULL_F_B16B16 1 "<sve_pred_fp_rhs1_operand>")
+          (match_operand:SVE_FULL_F_B16B16 2 "<sve_pred_fp_rhs2_operand>")]
          SVE_COND_FP_BINARY_OPTAB))]
   "TARGET_SVE && (<supports_bf16> || !<is_bf16>)"
   {
@@ -5589,30 +5589,30 @@
 
 ;; Predicated floating-point operations with merging.
 (define_expand "@cond_<optab><mode>"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand")
-       (unspec:SVE_FULL_F_BF
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand")
+       (unspec:SVE_FULL_F_B16B16
          [(match_operand:<VPRED> 1 "register_operand")
-          (unspec:SVE_FULL_F_BF
+          (unspec:SVE_FULL_F_B16B16
             [(match_dup 1)
              (const_int SVE_STRICT_GP)
-             (match_operand:SVE_FULL_F_BF 2 "<sve_pred_fp_rhs1_operand>")
-             (match_operand:SVE_FULL_F_BF 3 "<sve_pred_fp_rhs2_operand>")]
+             (match_operand:SVE_FULL_F_B16B16 2 "<sve_pred_fp_rhs1_operand>")
+             (match_operand:SVE_FULL_F_B16B16 3 "<sve_pred_fp_rhs2_operand>")]
             SVE_COND_FP_BINARY)
-          (match_operand:SVE_FULL_F_BF 4 "aarch64_simd_reg_or_zero")]
+          (match_operand:SVE_FULL_F_B16B16 4 "aarch64_simd_reg_or_zero")]
          UNSPEC_SEL))]
   "TARGET_SVE && (<supports_bf16> || !<is_bf16>)"
 )
 
 ;; Predicated floating-point operations, merging with the first input.
 (define_insn_and_rewrite "*cond_<optab><mode>_2_relaxed"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand")
-       (unspec:SVE_FULL_F_BF
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand")
+       (unspec:SVE_FULL_F_B16B16
          [(match_operand:<VPRED> 1 "register_operand")
-          (unspec:SVE_FULL_F_BF
+          (unspec:SVE_FULL_F_B16B16
             [(match_operand 4)
              (const_int SVE_RELAXED_GP)
-             (match_operand:SVE_FULL_F_BF 2 "register_operand")
-             (match_operand:SVE_FULL_F_BF 3 "register_operand")]
+             (match_operand:SVE_FULL_F_B16B16 2 "register_operand")
+             (match_operand:SVE_FULL_F_B16B16 3 "register_operand")]
             SVE_COND_FP_BINARY)
           (match_dup 2)]
          UNSPEC_SEL))]
@@ -5628,14 +5628,14 @@
 )
 
 (define_insn "*cond_<optab><mode>_2_strict"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand")
-       (unspec:SVE_FULL_F_BF
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand")
+       (unspec:SVE_FULL_F_B16B16
          [(match_operand:<VPRED> 1 "register_operand")
-          (unspec:SVE_FULL_F_BF
+          (unspec:SVE_FULL_F_B16B16
             [(match_dup 1)
              (const_int SVE_STRICT_GP)
-             (match_operand:SVE_FULL_F_BF 2 "register_operand")
-             (match_operand:SVE_FULL_F_BF 3 "register_operand")]
+             (match_operand:SVE_FULL_F_B16B16 2 "register_operand")
+             (match_operand:SVE_FULL_F_B16B16 3 "register_operand")]
             SVE_COND_FP_BINARY)
           (match_dup 2)]
          UNSPEC_SEL))]
@@ -5691,14 +5691,14 @@
 
 ;; Predicated floating-point operations, merging with the second input.
 (define_insn_and_rewrite "*cond_<optab><mode>_3_relaxed"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand")
-       (unspec:SVE_FULL_F_BF
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand")
+       (unspec:SVE_FULL_F_B16B16
          [(match_operand:<VPRED> 1 "register_operand")
-          (unspec:SVE_FULL_F_BF
+          (unspec:SVE_FULL_F_B16B16
             [(match_operand 4)
              (const_int SVE_RELAXED_GP)
-             (match_operand:SVE_FULL_F_BF 2 "register_operand")
-             (match_operand:SVE_FULL_F_BF 3 "register_operand")]
+             (match_operand:SVE_FULL_F_B16B16 2 "register_operand")
+             (match_operand:SVE_FULL_F_B16B16 3 "register_operand")]
             SVE_COND_FP_BINARY)
           (match_dup 3)]
          UNSPEC_SEL))]
@@ -5714,14 +5714,14 @@
 )
 
 (define_insn "*cond_<optab><mode>_3_strict"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand")
-       (unspec:SVE_FULL_F_BF
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand")
+       (unspec:SVE_FULL_F_B16B16
          [(match_operand:<VPRED> 1 "register_operand")
-          (unspec:SVE_FULL_F_BF
+          (unspec:SVE_FULL_F_B16B16
             [(match_dup 1)
              (const_int SVE_STRICT_GP)
-             (match_operand:SVE_FULL_F_BF 2 "register_operand")
-             (match_operand:SVE_FULL_F_BF 3 "register_operand")]
+             (match_operand:SVE_FULL_F_B16B16 2 "register_operand")
+             (match_operand:SVE_FULL_F_B16B16 3 "register_operand")]
             SVE_COND_FP_BINARY)
           (match_dup 3)]
          UNSPEC_SEL))]
@@ -5734,16 +5734,16 @@
 
 ;; Predicated floating-point operations, merging with an independent value.
 (define_insn_and_rewrite "*cond_<optab><mode>_any_relaxed"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand")
-       (unspec:SVE_FULL_F_BF
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand")
+       (unspec:SVE_FULL_F_B16B16
          [(match_operand:<VPRED> 1 "register_operand")
-          (unspec:SVE_FULL_F_BF
+          (unspec:SVE_FULL_F_B16B16
             [(match_operand 5)
              (const_int SVE_RELAXED_GP)
-             (match_operand:SVE_FULL_F_BF 2 "register_operand")
-             (match_operand:SVE_FULL_F_BF 3 "register_operand")]
+             (match_operand:SVE_FULL_F_B16B16 2 "register_operand")
+             (match_operand:SVE_FULL_F_B16B16 3 "register_operand")]
             SVE_COND_FP_BINARY)
-          (match_operand:SVE_FULL_F_BF 4 "aarch64_simd_reg_or_zero")]
+          (match_operand:SVE_FULL_F_B16B16 4 "aarch64_simd_reg_or_zero")]
          UNSPEC_SEL))]
   "TARGET_SVE
    && (<supports_bf16> || !<is_bf16>)
@@ -5778,16 +5778,16 @@
 )
 
 (define_insn_and_rewrite "*cond_<optab><mode>_any_strict"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand")
-       (unspec:SVE_FULL_F_BF
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand")
+       (unspec:SVE_FULL_F_B16B16
          [(match_operand:<VPRED> 1 "register_operand")
-          (unspec:SVE_FULL_F_BF
+          (unspec:SVE_FULL_F_B16B16
             [(match_dup 1)
              (const_int SVE_STRICT_GP)
-             (match_operand:SVE_FULL_F_BF 2 "register_operand")
-             (match_operand:SVE_FULL_F_BF 3 "register_operand")]
+             (match_operand:SVE_FULL_F_B16B16 2 "register_operand")
+             (match_operand:SVE_FULL_F_B16B16 3 "register_operand")]
             SVE_COND_FP_BINARY)
-          (match_operand:SVE_FULL_F_BF 4 "aarch64_simd_reg_or_zero")]
+          (match_operand:SVE_FULL_F_B16B16 4 "aarch64_simd_reg_or_zero")]
          UNSPEC_SEL))]
   "TARGET_SVE
    && (<supports_bf16> || !<is_bf16>)
@@ -6651,13 +6651,13 @@
 
 ;; Unpredicated multiplication by selected lanes.
 (define_insn "@aarch64_mul_lane_<mode>"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand" "=w")
-       (mult:SVE_FULL_F_BF
-         (unspec:SVE_FULL_F_BF
-           [(match_operand:SVE_FULL_F_BF 2 "register_operand" "<sve_lane_con>")
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand" "=w")
+       (mult:SVE_FULL_F_B16B16
+         (unspec:SVE_FULL_F_B16B16
+           [(match_operand:SVE_FULL_F_B16B16 2 "register_operand" "<sve_lane_con>")
             (match_operand:SI 3 "const_int_operand")]
            UNSPEC_SVE_LANE_SELECT)
-         (match_operand:SVE_FULL_F_BF 1 "register_operand" "w")))]
+         (match_operand:SVE_FULL_F_B16B16 1 "register_operand" "w")))]
   "TARGET_SVE"
   "<b>fmul\t%0.<Vetype>, %1.<Vetype>, %2.<Vetype>[%3]"
 )
@@ -6716,10 +6716,10 @@
 ;; by providing this, but we need to use UNSPECs since rtx logical ops
 ;; aren't defined for floating-point modes.
 (define_insn "*<optab><mode>3"
-  [(set (match_operand:SVE_F 0 "register_operand" "=w")
-       (unspec:SVE_F
-         [(match_operand:SVE_F 1 "register_operand" "w")
-          (match_operand:SVE_F 2 "register_operand" "w")]
+  [(set (match_operand:SVE_F_BF 0 "register_operand" "=w")
+       (unspec:SVE_F_BF
+         [(match_operand:SVE_F_BF 1 "register_operand" "w")
+          (match_operand:SVE_F_BF 2 "register_operand" "w")]
          LOGICALF))]
   "TARGET_SVE"
   "<logicalf_op>\t%0.d, %1.d, %2.d"
@@ -7579,13 +7579,13 @@
 
 ;; Unpredicated floating-point ternary operations.
 (define_expand "<optab><mode>4"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand")
-       (unspec:SVE_FULL_F_BF
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand")
+       (unspec:SVE_FULL_F_B16B16
          [(match_dup 4)
           (const_int SVE_RELAXED_GP)
-          (match_operand:SVE_FULL_F_BF 1 "register_operand")
-          (match_operand:SVE_FULL_F_BF 2 "register_operand")
-          (match_operand:SVE_FULL_F_BF 3 "register_operand")]
+          (match_operand:SVE_FULL_F_B16B16 1 "register_operand")
+          (match_operand:SVE_FULL_F_B16B16 2 "register_operand")
+          (match_operand:SVE_FULL_F_B16B16 3 "register_operand")]
          SVE_COND_FP_TERNARY))]
   "TARGET_SVE && (<supports_bf16> || !<is_bf16>)"
   {
@@ -7595,13 +7595,13 @@
 
 ;; Predicated floating-point ternary operations.
 (define_insn "@aarch64_pred_<optab><mode>"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand")
-       (unspec:SVE_FULL_F_BF
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand")
+       (unspec:SVE_FULL_F_B16B16
          [(match_operand:<VPRED> 1 "register_operand")
           (match_operand:SI 5 "aarch64_sve_gp_strictness")
-          (match_operand:SVE_FULL_F_BF 2 "register_operand")
-          (match_operand:SVE_FULL_F_BF 3 "register_operand")
-          (match_operand:SVE_FULL_F_BF 4 "register_operand")]
+          (match_operand:SVE_FULL_F_B16B16 2 "register_operand")
+          (match_operand:SVE_FULL_F_B16B16 3 "register_operand")
+          (match_operand:SVE_FULL_F_B16B16 4 "register_operand")]
          SVE_COND_FP_TERNARY))]
   "TARGET_SVE && (<supports_bf16> || !<is_bf16>)"
   {@ [ cons: =0 , 1   , %2  , 3 , 4 ; attrs: movprfx , is_rev ]
@@ -7615,17 +7615,17 @@
 
 ;; Predicated floating-point ternary operations with merging.
 (define_expand "@cond_<optab><mode>"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand")
-       (unspec:SVE_FULL_F_BF
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand")
+       (unspec:SVE_FULL_F_B16B16
          [(match_operand:<VPRED> 1 "register_operand")
-          (unspec:SVE_FULL_F_BF
+          (unspec:SVE_FULL_F_B16B16
             [(match_dup 1)
              (const_int SVE_STRICT_GP)
-             (match_operand:SVE_FULL_F_BF 2 "register_operand")
-             (match_operand:SVE_FULL_F_BF 3 "register_operand")
-             (match_operand:SVE_FULL_F_BF 4 "register_operand")]
+             (match_operand:SVE_FULL_F_B16B16 2 "register_operand")
+             (match_operand:SVE_FULL_F_B16B16 3 "register_operand")
+             (match_operand:SVE_FULL_F_B16B16 4 "register_operand")]
             SVE_COND_FP_TERNARY)
-          (match_operand:SVE_FULL_F_BF 5 "aarch64_simd_reg_or_zero")]
+          (match_operand:SVE_FULL_F_B16B16 5 "aarch64_simd_reg_or_zero")]
          UNSPEC_SEL))]
   "TARGET_SVE && (<supports_bf16> || !<is_bf16>)"
 {
@@ -7684,15 +7684,15 @@
 ;; Predicated floating-point ternary operations, merging with the
 ;; third input.
 (define_insn_and_rewrite "*cond_<optab><mode>_4_relaxed"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand")
-       (unspec:SVE_FULL_F_BF
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand")
+       (unspec:SVE_FULL_F_B16B16
          [(match_operand:<VPRED> 1 "register_operand")
-          (unspec:SVE_FULL_F_BF
+          (unspec:SVE_FULL_F_B16B16
             [(match_operand 5)
              (const_int SVE_RELAXED_GP)
-             (match_operand:SVE_FULL_F_BF 2 "register_operand")
-             (match_operand:SVE_FULL_F_BF 3 "register_operand")
-             (match_operand:SVE_FULL_F_BF 4 "register_operand")]
+             (match_operand:SVE_FULL_F_B16B16 2 "register_operand")
+             (match_operand:SVE_FULL_F_B16B16 3 "register_operand")
+             (match_operand:SVE_FULL_F_B16B16 4 "register_operand")]
             SVE_COND_FP_TERNARY)
           (match_dup 4)]
          UNSPEC_SEL))]
@@ -7708,15 +7708,15 @@
 )
 
 (define_insn "*cond_<optab><mode>_4_strict"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand")
-       (unspec:SVE_FULL_F_BF
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand")
+       (unspec:SVE_FULL_F_B16B16
          [(match_operand:<VPRED> 1 "register_operand")
-          (unspec:SVE_FULL_F_BF
+          (unspec:SVE_FULL_F_B16B16
             [(match_dup 1)
              (const_int SVE_STRICT_GP)
-             (match_operand:SVE_FULL_F_BF 2 "register_operand")
-             (match_operand:SVE_FULL_F_BF 3 "register_operand")
-             (match_operand:SVE_FULL_F_BF 4 "register_operand")]
+             (match_operand:SVE_FULL_F_B16B16 2 "register_operand")
+             (match_operand:SVE_FULL_F_B16B16 3 "register_operand")
+             (match_operand:SVE_FULL_F_B16B16 4 "register_operand")]
             SVE_COND_FP_TERNARY)
           (match_dup 4)]
          UNSPEC_SEL))]
@@ -7730,17 +7730,17 @@
 ;; Predicated floating-point ternary operations, merging with an
 ;; independent value.
 (define_insn_and_rewrite "*cond_<optab><mode>_any_relaxed"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand")
-       (unspec:SVE_FULL_F_BF
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand")
+       (unspec:SVE_FULL_F_B16B16
          [(match_operand:<VPRED> 1 "register_operand")
-          (unspec:SVE_FULL_F_BF
+          (unspec:SVE_FULL_F_B16B16
             [(match_operand 6)
              (const_int SVE_RELAXED_GP)
-             (match_operand:SVE_FULL_F_BF 2 "register_operand")
-             (match_operand:SVE_FULL_F_BF 3 "register_operand")
-             (match_operand:SVE_FULL_F_BF 4 "register_operand")]
+             (match_operand:SVE_FULL_F_B16B16 2 "register_operand")
+             (match_operand:SVE_FULL_F_B16B16 3 "register_operand")
+             (match_operand:SVE_FULL_F_B16B16 4 "register_operand")]
             SVE_COND_FP_TERNARY)
-          (match_operand:SVE_FULL_F_BF 5 "aarch64_simd_reg_or_zero")]
+          (match_operand:SVE_FULL_F_B16B16 5 "aarch64_simd_reg_or_zero")]
          UNSPEC_SEL))]
   "TARGET_SVE
    && (<supports_bf16> || !<is_bf16>)
@@ -7776,17 +7776,17 @@
 )
 
 (define_insn_and_rewrite "*cond_<optab><mode>_any_strict"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand")
-       (unspec:SVE_FULL_F_BF
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand")
+       (unspec:SVE_FULL_F_B16B16
          [(match_operand:<VPRED> 1 "register_operand")
-          (unspec:SVE_FULL_F_BF
+          (unspec:SVE_FULL_F_B16B16
             [(match_dup 1)
              (const_int SVE_STRICT_GP)
-             (match_operand:SVE_FULL_F_BF 2 "register_operand")
-             (match_operand:SVE_FULL_F_BF 3 "register_operand")
-             (match_operand:SVE_FULL_F_BF 4 "register_operand")]
+             (match_operand:SVE_FULL_F_B16B16 2 "register_operand")
+             (match_operand:SVE_FULL_F_B16B16 3 "register_operand")
+             (match_operand:SVE_FULL_F_B16B16 4 "register_operand")]
             SVE_COND_FP_TERNARY)
-          (match_operand:SVE_FULL_F_BF 5 "aarch64_simd_reg_or_zero")]
+          (match_operand:SVE_FULL_F_B16B16 5 "aarch64_simd_reg_or_zero")]
          UNSPEC_SEL))]
   "TARGET_SVE
    && (<supports_bf16> || !<is_bf16>)
@@ -7817,14 +7817,14 @@
 ;; Unpredicated FMLA and FMLS by selected lanes.  It doesn't seem worth using
 ;; (fma ...) since target-independent code won't understand the indexing.
 (define_insn "@aarch64_<optab>_lane_<mode>"
-  [(set (match_operand:SVE_FULL_F_BF 0 "register_operand")
-       (unspec:SVE_FULL_F_BF
-         [(match_operand:SVE_FULL_F_BF 1 "register_operand")
-          (unspec:SVE_FULL_F_BF
-            [(match_operand:SVE_FULL_F_BF 2 "register_operand")
+  [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand")
+       (unspec:SVE_FULL_F_B16B16
+         [(match_operand:SVE_FULL_F_B16B16 1 "register_operand")
+          (unspec:SVE_FULL_F_B16B16
+            [(match_operand:SVE_FULL_F_B16B16 2 "register_operand")
              (match_operand:SI 3 "const_int_operand")]
             UNSPEC_SVE_LANE_SELECT)
-          (match_operand:SVE_FULL_F_BF 4 "register_operand")]
+          (match_operand:SVE_FULL_F_B16B16 4 "register_operand")]
          SVE_FP_TERNARY_LANE))]
   "TARGET_SVE"
   {@ [ cons: =0 , 1 , 2              , 4 ; attrs: movprfx ]

diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 146453b0516848acd40e5f34fd8843fe74c18dbf..d629538775178df4daeb6cead29535a2e4eb98af 100644 (file)
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -479,13 +479,25 @@
 ;; All fully-packed SVE integer and Advanced SIMD integer modes.
 (define_mode_iterator SVE_ASIMD_FULL_I [SVE_FULL_I VDQ_I])
 
-;; All fully-packed SVE floating-point vector modes.
+;; Fully-packed SVE floating-point vector modes, excluding BF16.
 (define_mode_iterator SVE_FULL_F [VNx8HF VNx4SF VNx2DF])
 
+;; Partial SVE floating-point vector modes, excluding BF16.
+(define_mode_iterator SVE_PARTIAL_F [VNx2HF VNx4HF VNx2SF])
+
+;; SVE floating-point vector modes, excluding BF16.
+(define_mode_iterator SVE_F [SVE_PARTIAL_F SVE_FULL_F])
+
 ;; Fully-packed SVE floating-point vector modes and their scalar equivalents.
 (define_mode_iterator SVE_FULL_F_SCALAR [SVE_FULL_F GPF_HF])
 
-(define_mode_iterator SVE_FULL_F_BF [(VNx8BF "TARGET_SSVE_B16B16") SVE_FULL_F])
+(define_mode_iterator SVE_FULL_F_B16B16 [(VNx8BF "TARGET_SSVE_B16B16") SVE_FULL_F])
+
+(define_mode_iterator SVE_PARTIAL_F_B16B16 [(VNx2BF "TARGET_SSVE_B16B16")
+                                           (VNx4BF "TARGET_SSVE_B16B16")
+                                           SVE_PARTIAL_F])
+
+(define_mode_iterator SVE_F_B16B16 [SVE_PARTIAL_F_B16B16 SVE_FULL_F_B16B16])
 
 ;; Modes for which (B)FCLAMP is supported.
 (define_mode_iterator SVE_CLAMP_F [(VNx8BF "TARGET_SSVE_B16B16")
@@ -580,14 +592,13 @@
                             VNx4SI VNx2SI
                             VNx2DI])
 
+(define_mode_iterator SVE_BF [VNx2BF VNx4BF VNx8BF])
+
 ;; All SVE floating-point vector modes.
-(define_mode_iterator SVE_F [VNx8HF VNx4HF VNx2HF
-                            VNx8BF VNx4BF VNx2BF
-                            VNx4SF VNx2SF
-                            VNx2DF])
+(define_mode_iterator SVE_F_BF [SVE_F SVE_BF])
 
 ;; All SVE vector modes.
-(define_mode_iterator SVE_ALL [SVE_I SVE_F])
+(define_mode_iterator SVE_ALL [SVE_I SVE_F_BF])
 
 ;; All SVE 2-vector modes.
 (define_mode_iterator SVE_FULLx2 [VNx32QI VNx16HI VNx8SI VNx4DI
@@ -2445,7 +2456,9 @@
                           (VNx8DI "vnx2di") (VNx8DF "vnx2df")])
 
 ;; The predicate mode associated with an SVE data mode.  For structure modes
-;; this is equivalent to the <VPRED> of the subvector mode.
+;; this is equivalent to the <VPRED> of the subvector mode.  For partial
+;; vector modes, this is equivalent to the <VPRED> of a full SVE mode with
+;; the same number of elements.
 (define_mode_attr VPRED [(VNx16QI "VNx16BI") (VNx8QI "VNx8BI")
                         (VNx4QI "VNx4BI") (VNx2QI "VNx2BI")
                         (VNx8HI "VNx8BI") (VNx4HI "VNx4BI") (VNx2HI "VNx2BI")
@@ -2611,13 +2624,15 @@
                                 (V2DI "vec") (DI "offset")])
 
 (define_mode_attr b [(V4BF "b") (V4HF "") (V8BF "b") (V8HF "")
-                    (VNx8BF "b") (VNx8HF "") (VNx4SF "") (VNx2DF "")
+                    (VNx2BF "b") (VNx2HF "") (VNx2SF "")
+                    (VNx4BF "b") (VNx4HF "") (VNx4SF "")
+                    (VNx8BF "b") (VNx8HF "") (VNx2DF "")
                     (VNx16BF "b") (VNx16HF "") (VNx8SF "") (VNx4DF "")
                     (VNx32BF "b") (VNx32HF "") (VNx16SF "") (VNx8DF "")])
 
-(define_mode_attr is_bf16 [(VNx8BF "true")
-                          (VNx8HF "false")
-                          (VNx4SF "false")
+(define_mode_attr is_bf16 [(VNx2BF "true") (VNx4BF "true") (VNx8BF "true")
+                          (VNx2HF "false") (VNx4HF "false") (VNx8HF "false")
+                          (VNx2SF "false") (VNx4SF "false")
                           (VNx2DF "false")])
 
 (define_mode_attr aligned_operand [(VNx16QI "register_operand")