MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
}
-static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
+static int scpsys_bus_protect_enable(struct scpsys_domain *pd, u8 flags)
{
for (int i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) {
const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i];
if (!bpd->bus_prot_set_clr_mask)
break;
+ if ((bpd->flags & BUS_PROT_IGNORE_SUBCLK) !=
+ (flags & BUS_PROT_IGNORE_SUBCLK))
+ continue;
+
if (bpd->flags & BUS_PROT_INVERTED)
ret = scpsys_bus_protect_clear(pd, bpd);
else
return 0;
}
-static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
+static int scpsys_bus_protect_disable(struct scpsys_domain *pd, u8 flags)
{
for (int i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) {
const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i];
if (!bpd->bus_prot_set_clr_mask)
continue;
+ if ((bpd->flags & BUS_PROT_IGNORE_SUBCLK) !=
+ (flags & BUS_PROT_IGNORE_SUBCLK))
+ continue;
+
if (bpd->flags & BUS_PROT_INVERTED)
ret = scpsys_bus_protect_set(pd, bpd);
else
if (ret)
goto err_pwr_ack;
+ /*
+ * In MT8189 mminfra power domain, the bus protect policy separates
+ * into two parts, one is set before subsys clocks enabled, and another
+ * need to enable after subsys clocks enable.
+ */
+ ret = scpsys_bus_protect_disable(pd, BUS_PROT_IGNORE_SUBCLK);
+ if (ret < 0)
+ goto err_pwr_ack;
+
/*
* In few Mediatek platforms(e.g. MT6779), the bus protect policy is
* stricter, which leads to bus protect release must be prior to bus
if (ret < 0)
goto err_disable_subsys_clks;
- ret = scpsys_bus_protect_disable(pd);
+ ret = scpsys_bus_protect_disable(pd, 0);
if (ret < 0)
goto err_disable_sram;
return 0;
err_enable_bus_protect:
- scpsys_bus_protect_enable(pd);
+ scpsys_bus_protect_enable(pd, 0);
err_disable_sram:
scpsys_sram_disable(pd);
err_disable_subsys_clks:
bool tmp;
int ret;
- ret = scpsys_bus_protect_enable(pd);
+ ret = scpsys_bus_protect_enable(pd, 0);
if (ret < 0)
return ret;
clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
+ ret = scpsys_bus_protect_enable(pd, BUS_PROT_IGNORE_SUBCLK);
+ if (ret < 0)
+ return ret;
+
if (MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_PWRSEQ))
scpsys_modem_pwrseq_off(pd);
else
BUS_PROT_REG_UPDATE = BIT(1),
BUS_PROT_IGNORE_CLR_ACK = BIT(2),
BUS_PROT_INVERTED = BIT(3),
+ BUS_PROT_IGNORE_SUBCLK = BIT(4),
};
enum scpsys_bus_prot_block {
_BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \
BUS_PROT_REG_UPDATE)
+#define BUS_PROT_WR_IGN_SUBCLK(_hwip, _mask, _set, _clr, _sta) \
+ _BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \
+ BUS_PROT_IGNORE_CLR_ACK | BUS_PROT_IGNORE_SUBCLK)
+
#define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \
BUS_PROT_UPDATE(INFRA, _mask, \
INFRA_TOPAXI_PROTECTEN, \