]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
dt-bindings: clock: qcom: Add CMN PLL support for IPQ5332 SoC
authorLuo Jie <jie.luo@oss.qualcomm.com>
Wed, 7 Jan 2026 05:35:11 +0000 (21:35 -0800)
committerBjorn Andersson <andersson@kernel.org>
Tue, 12 May 2026 20:31:20 +0000 (15:31 -0500)
Add device tree bindings for the CMN PLL block in IPQ5332 SoC, which shares
similarities with IPQ9574 but has different output clock frequencies.

Add a new header file to export CMN PLL output clock specifiers for IPQ5332
SoC.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260106-qcom_ipq5332_cmnpll-v2-2-f9f7e4efbd79@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
include/dt-bindings/clock/qcom,ipq5332-cmn-pll.h [new file with mode: 0644]

index de338c05190fb1ce7bc7e70b7866e6c4766ac28e..b9c3650e5c4cb53bd7e6987fd111a6b00e64a29c 100644 (file)
@@ -25,6 +25,7 @@ properties:
   compatible:
     enum:
       - qcom,ipq5018-cmn-pll
+      - qcom,ipq5332-cmn-pll
       - qcom,ipq5424-cmn-pll
       - qcom,ipq6018-cmn-pll
       - qcom,ipq8074-cmn-pll
diff --git a/include/dt-bindings/clock/qcom,ipq5332-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq5332-cmn-pll.h
new file mode 100644 (file)
index 0000000..172330e
--- /dev/null
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5332_CMN_PLL_H
+#define _DT_BINDINGS_CLK_QCOM_IPQ5332_CMN_PLL_H
+
+/* CMN PLL core clock. */
+#define IPQ5332_CMN_PLL_CLK                    0
+
+/* The output clocks from CMN PLL of IPQ5332. */
+#define IPQ5332_XO_24MHZ_CLK                   1
+#define IPQ5332_SLEEP_32KHZ_CLK                        2
+#define IPQ5332_PCS_31P25MHZ_CLK               3
+#define IPQ5332_NSS_300MHZ_CLK                 4
+#define IPQ5332_PPE_200MHZ_CLK                 5
+#define IPQ5332_ETH_50MHZ_CLK                  6
+#endif