drivers/perf: hisi: Relax the event number check of v2 PMUs

The supported event number range of each Uncore PMUs is provided by
each driver in hisi_pmu::check_event and out of range events
will be rejected. A later version with expanded event number range
needs to register the PMU with updated hisi_pmu::check_event
even if it's the only update, which means the expanded events
cannot be used unless the driver's updated. However the unsupported
events won't be counted by the hardware so we can relax the event
number check to allow the use the expanded events.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Junhao He <hejunhao3@huawei.com>
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Link: https://lore.kernel.org/r/20250619125557.57372-6-yangyicong@huawei.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c b/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
index 26eaa6d20c0009c858247ac2ec7303b49d550bfe..21c494881ca04bfcbc5aa72a917cc9bf4fdac13b 100644 (file)
--- a/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
+++ b/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
@@ -53,7 +53,7 @@
 #define DDRC_V1_PERF_CTRL_EN   0x2
 #define DDRC_V2_PERF_CTRL_EN   0x1
 #define DDRC_V1_NR_EVENTS      0x7
-#define DDRC_V2_NR_EVENTS      0x90
+#define DDRC_V2_NR_EVENTS      0xFF
 
 #define DDRC_EVENT_CNTn(base, n)       ((base) + (n) * 8)
 #define DDRC_EVENT_TYPEn(base, n)      ((base) + (n) * 4)

diff --git a/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c b/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
index ca609db860460497aebc4b92a4ce0537775fe9cf..97cfaa586a87a78b573f980297b92aa9d8ded6a5 100644 (file)
--- a/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
+++ b/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
@@ -47,9 +47,9 @@
 #define HHA_SRCID_CMD          GENMASK(16, 6)
 #define HHA_SRCID_MSK          GENMASK(30, 20)
 #define HHA_DATSRC_SKT_EN      BIT(23)
-#define HHA_EVTYPE_NONE                0xff
+#define HHA_EVTYPE_MASK                GENMASK(7, 0)
 #define HHA_V1_NR_EVENT                0x65
-#define HHA_V2_NR_EVENT                0xCE
+#define HHA_V2_NR_EVENT                0xFF
 
 HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_cmd, config1, 10, 0);
 HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_msk, config1, 21, 11);
@@ -197,7 +197,7 @@ static void hisi_hha_pmu_write_evtype(struct hisi_pmu *hha_pmu, int idx,
 
        /* Write event code to HHA_EVENT_TYPEx register */
        val = readl(hha_pmu->base + reg);
-       val &= ~(HHA_EVTYPE_NONE << shift);
+       val &= ~(HHA_EVTYPE_MASK << shift);
        val |= (type << shift);
        writel(val, hha_pmu->base + reg);
 }

diff --git a/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
index a0142684e37918a2f4c35785018298ed3ae51cbd..80108c63cb6050edcbff884ae6a84a99d9ac2ad8 100644 (file)
--- a/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
+++ b/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
@@ -440,7 +440,7 @@ static int hisi_pa_pmu_dev_probe(struct platform_device *pdev,
        pa_pmu->pmu_events.attr_groups = pa_pmu->dev_info->attr_groups;
        pa_pmu->num_counters = PA_NR_COUNTERS;
        pa_pmu->ops = &hisi_uncore_pa_ops;
-       pa_pmu->check_event = 0xB0;
+       pa_pmu->check_event = PA_EVTYPE_MASK;
        pa_pmu->counter_bits = 64;
        pa_pmu->dev = &pdev->dev;
        pa_pmu->on_cpu = -1;

diff --git a/drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c b/drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
index 852114cfe3bffefabf9cd0466c43b56a6aaa9a58..cd32d606df0548991168e8c411aa251a02b6a8d6 100644 (file)
--- a/drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
+++ b/drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
@@ -58,7 +58,7 @@
 #define SLLC_V3_SRCID_CMD_SHIFT                1
 #define SLLC_V3_SRCID_MSK_SHIFT                10
 
-#define SLLC_NR_EVENTS                 0x80
+#define SLLC_NR_EVENTS                 0xff
 #define SLLC_EVENT_CNTn(cnt0, n)       ((cnt0) + (n) * 8)
 
 HISI_PMU_EVENT_ATTR_EXTRACTOR(tgtid_min, config1, 10, 0);