+++ /dev/null
-From 9773c540441c6ae15aefb49e67142e94369dbbc0 Mon Sep 17 00:00:00 2001
-From: Caleb James DeLisle <cjd@cjdns.fr>
-Date: Sun, 30 Mar 2025 17:02:58 +0000
-Subject: [PATCH] dt-bindings: interrupt-controller: Add EcoNet EN751221 INTC
-
-Document the device tree binding for the interrupt controller in the
-EcoNet EN751221 MIPS SoC.
-
-Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
-Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
-Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
-Link: https://lore.kernel.org/all/20250330170306.2584136-3-cjd@cjdns.fr
----
- .../econet,en751221-intc.yaml | 78 +++++++++++++++++++
- 1 file changed, 78 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml
-@@ -0,0 +1,78 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/interrupt-controller/econet,en751221-intc.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: EcoNet EN751221 Interrupt Controller
-+
-+maintainers:
-+ - Caleb James DeLisle <cjd@cjdns.fr>
-+
-+description:
-+ The EcoNet EN751221 Interrupt Controller is a simple interrupt controller
-+ designed for the MIPS 34Kc MT SMP processor with 2 VPEs. Each interrupt can
-+ be routed to either VPE but not both, so to support per-CPU interrupts, a
-+ secondary IRQ number is allocated to control masking/unmasking on VPE#1. For
-+ lack of a better term we call these "shadow interrupts". The assignment of
-+ shadow interrupts is defined by the SoC integrator when wiring the interrupt
-+ lines, so they are configurable in the device tree.
-+
-+allOf:
-+ - $ref: /schemas/interrupt-controller.yaml#
-+
-+properties:
-+ compatible:
-+ const: econet,en751221-intc
-+
-+ reg:
-+ maxItems: 1
-+
-+ "#interrupt-cells":
-+ const: 1
-+
-+ interrupt-controller: true
-+
-+ interrupts:
-+ maxItems: 1
-+ description: Interrupt line connecting this controller to its parent.
-+
-+ econet,shadow-interrupts:
-+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
-+ description:
-+ An array of interrupt number pairs where each pair represents a shadow
-+ interrupt relationship. The first number in each pair is the primary IRQ,
-+ and the second is its shadow IRQ used for VPE#1 control. For example,
-+ <8 3> means IRQ 8 is shadowed by IRQ 3, so IRQ 3 cannot be mapped, but
-+ when VPE#1 requests IRQ 8, it will manipulate the IRQ 3 mask bit.
-+ minItems: 1
-+ maxItems: 20
-+ items:
-+ items:
-+ - description: primary per-CPU IRQ
-+ - description: shadow IRQ number
-+
-+required:
-+ - compatible
-+ - reg
-+ - interrupt-controller
-+ - "#interrupt-cells"
-+ - interrupts
-+
-+additionalProperties: false
-+
-+examples:
-+ - |
-+ interrupt-controller@1fb40000 {
-+ compatible = "econet,en751221-intc";
-+ reg = <0x1fb40000 0x100>;
-+
-+ interrupt-controller;
-+ #interrupt-cells = <1>;
-+
-+ interrupt-parent = <&cpuintc>;
-+ interrupts = <2>;
-+
-+ econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;
-+ };
-+...
+++ /dev/null
-From 1902a59cf5f9d8b99ecf0cb8f122cb00ef7a3f13 Mon Sep 17 00:00:00 2001
-From: Caleb James DeLisle <cjd@cjdns.fr>
-Date: Sun, 30 Mar 2025 17:02:59 +0000
-Subject: [PATCH] irqchip: Add EcoNet EN751221 INTC
-
-Add a driver for the interrupt controller in the EcoNet EN751221 MIPS SoC.
-
-Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
-Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
-Link: https://lore.kernel.org/all/20250330170306.2584136-4-cjd@cjdns.fr
----
- drivers/irqchip/Kconfig | 5 +
- drivers/irqchip/Makefile | 1 +
- drivers/irqchip/irq-econet-en751221.c | 309 ++++++++++++++++++++++++++
- 3 files changed, 315 insertions(+)
- create mode 100644 drivers/irqchip/irq-econet-en751221.c
-
---- a/drivers/irqchip/Kconfig
-+++ b/drivers/irqchip/Kconfig
-@@ -148,6 +148,11 @@ config DW_APB_ICTL
- select GENERIC_IRQ_CHIP
- select IRQ_DOMAIN_HIERARCHY
-
-+config ECONET_EN751221_INTC
-+ bool
-+ select GENERIC_IRQ_CHIP
-+ select IRQ_DOMAIN
-+
- config FARADAY_FTINTC010
- bool
- select IRQ_DOMAIN
---- a/drivers/irqchip/Makefile
-+++ b/drivers/irqchip/Makefile
-@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_BCM2835) += irq-bcm28
- obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o
- obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o
- obj-$(CONFIG_EXYNOS_IRQ_COMBINER) += exynos-combiner.o
-+obj-$(CONFIG_ECONET_EN751221_INTC) += irq-econet-en751221.o
- obj-$(CONFIG_FARADAY_FTINTC010) += irq-ftintc010.o
- obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
- obj-$(CONFIG_ARCH_LPC32XX) += irq-lpc32xx.o
---- /dev/null
-+++ b/drivers/irqchip/irq-econet-en751221.c
-@@ -0,0 +1,309 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * EN751221 Interrupt Controller Driver.
-+ *
-+ * The EcoNet EN751221 Interrupt Controller is a simple interrupt controller
-+ * designed for the MIPS 34Kc MT SMP processor with 2 VPEs. Each interrupt can
-+ * be routed to either VPE but not both, so to support per-CPU interrupts, a
-+ * secondary IRQ number is allocated to control masking/unmasking on VPE#1. In
-+ * this driver, these are called "shadow interrupts". The assignment of shadow
-+ * interrupts is defined by the SoC integrator when wiring the interrupt lines,
-+ * so they are configurable in the device tree.
-+ *
-+ * If an interrupt (say 30) needs per-CPU capability, the SoC integrator
-+ * allocates another IRQ number (say 29) to be its shadow. The device tree
-+ * reflects this by adding the pair <30 29> to the "econet,shadow-interrupts"
-+ * property.
-+ *
-+ * When VPE#1 requests IRQ 30, the driver manipulates the mask bit for IRQ 29,
-+ * telling the hardware to mask VPE#1's view of IRQ 30.
-+ *
-+ * Copyright (C) 2025 Caleb James DeLisle <cjd@cjdns.fr>
-+ */
-+
-+#include <linux/cleanup.h>
-+#include <linux/io.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_irq.h>
-+#include <linux/irqdomain.h>
-+#include <linux/irqchip.h>
-+#include <linux/irqchip/chained_irq.h>
-+
-+#define IRQ_COUNT 40
-+
-+#define NOT_PERCPU 0xff
-+#define IS_SHADOW 0xfe
-+
-+#define REG_MASK0 0x04
-+#define REG_MASK1 0x50
-+#define REG_PENDING0 0x08
-+#define REG_PENDING1 0x54
-+
-+/**
-+ * @membase: Base address of the interrupt controller registers
-+ * @interrupt_shadows: Array of all interrupts, for each value,
-+ * - NOT_PERCPU: This interrupt is not per-cpu, so it has no shadow
-+ * - IS_SHADOW: This interrupt is a shadow of another per-cpu interrupt
-+ * - else: This is a per-cpu interrupt whose shadow is the value
-+ */
-+static struct {
-+ void __iomem *membase;
-+ u8 interrupt_shadows[IRQ_COUNT];
-+} econet_intc __ro_after_init;
-+
-+static DEFINE_RAW_SPINLOCK(irq_lock);
-+
-+/* IRQs must be disabled */
-+static void econet_wreg(u32 reg, u32 val, u32 mask)
-+{
-+ u32 v;
-+
-+ guard(raw_spinlock)(&irq_lock);
-+
-+ v = ioread32(econet_intc.membase + reg);
-+ v &= ~mask;
-+ v |= val & mask;
-+ iowrite32(v, econet_intc.membase + reg);
-+}
-+
-+/* IRQs must be disabled */
-+static void econet_chmask(u32 hwirq, bool unmask)
-+{
-+ u32 reg, mask;
-+ u8 shadow;
-+
-+ /*
-+ * If the IRQ is a shadow, it should never be manipulated directly.
-+ * It should only be masked/unmasked as a result of the "real" per-cpu
-+ * irq being manipulated by a thread running on VPE#1.
-+ * If it is per-cpu (has a shadow), and we're on VPE#1, the shadow is what we mask.
-+ * This is single processor only, so smp_processor_id() never exceeds 1.
-+ */
-+ shadow = econet_intc.interrupt_shadows[hwirq];
-+ if (WARN_ON_ONCE(shadow == IS_SHADOW))
-+ return;
-+ else if (shadow != NOT_PERCPU && smp_processor_id() == 1)
-+ hwirq = shadow;
-+
-+ if (hwirq >= 32) {
-+ reg = REG_MASK1;
-+ mask = BIT(hwirq - 32);
-+ } else {
-+ reg = REG_MASK0;
-+ mask = BIT(hwirq);
-+ }
-+
-+ econet_wreg(reg, unmask ? mask : 0, mask);
-+}
-+
-+/* IRQs must be disabled */
-+static void econet_intc_mask(struct irq_data *d)
-+{
-+ econet_chmask(d->hwirq, false);
-+}
-+
-+/* IRQs must be disabled */
-+static void econet_intc_unmask(struct irq_data *d)
-+{
-+ econet_chmask(d->hwirq, true);
-+}
-+
-+static void econet_mask_all(void)
-+{
-+ /* IRQs are generally disabled during init, but guarding here makes it non-obligatory. */
-+ guard(irqsave)();
-+ econet_wreg(REG_MASK0, 0, ~0);
-+ econet_wreg(REG_MASK1, 0, ~0);
-+}
-+
-+static void econet_intc_handle_pending(struct irq_domain *d, u32 pending, u32 offset)
-+{
-+ int hwirq;
-+
-+ while (pending) {
-+ hwirq = fls(pending) - 1;
-+ generic_handle_domain_irq(d, hwirq + offset);
-+ pending &= ~BIT(hwirq);
-+ }
-+}
-+
-+static void econet_intc_from_parent(struct irq_desc *desc)
-+{
-+ struct irq_chip *chip = irq_desc_get_chip(desc);
-+ struct irq_domain *domain;
-+ u32 pending0, pending1;
-+
-+ chained_irq_enter(chip, desc);
-+
-+ pending0 = ioread32(econet_intc.membase + REG_PENDING0);
-+ pending1 = ioread32(econet_intc.membase + REG_PENDING1);
-+
-+ if (unlikely(!(pending0 | pending1))) {
-+ spurious_interrupt();
-+ } else {
-+ domain = irq_desc_get_handler_data(desc);
-+ econet_intc_handle_pending(domain, pending0, 0);
-+ econet_intc_handle_pending(domain, pending1, 32);
-+ }
-+
-+ chained_irq_exit(chip, desc);
-+}
-+
-+static const struct irq_chip econet_irq_chip;
-+
-+static int econet_intc_map(struct irq_domain *d, u32 irq, irq_hw_number_t hwirq)
-+{
-+ int ret;
-+
-+ if (hwirq >= IRQ_COUNT) {
-+ pr_err("%s: hwirq %lu out of range\n", __func__, hwirq);
-+ return -EINVAL;
-+ } else if (econet_intc.interrupt_shadows[hwirq] == IS_SHADOW) {
-+ pr_err("%s: can't map hwirq %lu, it is a shadow interrupt\n", __func__, hwirq);
-+ return -EINVAL;
-+ }
-+
-+ if (econet_intc.interrupt_shadows[hwirq] == NOT_PERCPU) {
-+ irq_set_chip_and_handler(irq, &econet_irq_chip, handle_level_irq);
-+ } else {
-+ irq_set_chip_and_handler(irq, &econet_irq_chip, handle_percpu_devid_irq);
-+ ret = irq_set_percpu_devid(irq);
-+ if (ret)
-+ pr_warn("%s: Failed irq_set_percpu_devid for %u: %d\n", d->name, irq, ret);
-+ }
-+
-+ irq_set_chip_data(irq, NULL);
-+ return 0;
-+}
-+
-+static const struct irq_chip econet_irq_chip = {
-+ .name = "en751221-intc",
-+ .irq_unmask = econet_intc_unmask,
-+ .irq_mask = econet_intc_mask,
-+ .irq_mask_ack = econet_intc_mask,
-+};
-+
-+static const struct irq_domain_ops econet_domain_ops = {
-+ .xlate = irq_domain_xlate_onecell,
-+ .map = econet_intc_map
-+};
-+
-+static int __init get_shadow_interrupts(struct device_node *node)
-+{
-+ const char *field = "econet,shadow-interrupts";
-+ int num_shadows;
-+
-+ num_shadows = of_property_count_u32_elems(node, field);
-+
-+ memset(econet_intc.interrupt_shadows, NOT_PERCPU,
-+ sizeof(econet_intc.interrupt_shadows));
-+
-+ if (num_shadows <= 0) {
-+ return 0;
-+ } else if (num_shadows % 2) {
-+ pr_err("%pOF: %s count is odd, ignoring\n", node, field);
-+ return 0;
-+ }
-+
-+ u32 *shadows __free(kfree) = kmalloc_array(num_shadows, sizeof(u32), GFP_KERNEL);
-+ if (!shadows)
-+ return -ENOMEM;
-+
-+ if (of_property_read_u32_array(node, field, shadows, num_shadows)) {
-+ pr_err("%pOF: Failed to read %s\n", node, field);
-+ return -EINVAL;
-+ }
-+
-+ for (int i = 0; i < num_shadows; i += 2) {
-+ u32 shadow = shadows[i + 1];
-+ u32 target = shadows[i];
-+
-+ if (shadow > IRQ_COUNT) {
-+ pr_err("%pOF: %s[%d] shadow(%d) out of range\n",
-+ node, field, i + 1, shadow);
-+ continue;
-+ }
-+
-+ if (target >= IRQ_COUNT) {
-+ pr_err("%pOF: %s[%d] target(%d) out of range\n", node, field, i, target);
-+ continue;
-+ }
-+
-+ if (econet_intc.interrupt_shadows[target] != NOT_PERCPU) {
-+ pr_err("%pOF: %s[%d] target(%d) already has a shadow\n",
-+ node, field, i, target);
-+ continue;
-+ }
-+
-+ if (econet_intc.interrupt_shadows[shadow] != NOT_PERCPU) {
-+ pr_err("%pOF: %s[%d] shadow(%d) already has a target\n",
-+ node, field, i + 1, shadow);
-+ continue;
-+ }
-+
-+ econet_intc.interrupt_shadows[target] = shadow;
-+ econet_intc.interrupt_shadows[shadow] = IS_SHADOW;
-+ }
-+
-+ return 0;
-+}
-+
-+static int __init econet_intc_of_init(struct device_node *node, struct device_node *parent)
-+{
-+ struct irq_domain *domain;
-+ struct resource res;
-+ int ret, irq;
-+
-+ ret = get_shadow_interrupts(node);
-+ if (ret)
-+ return ret;
-+
-+ irq = irq_of_parse_and_map(node, 0);
-+ if (!irq) {
-+ pr_err("%pOF: DT: Failed to get IRQ from 'interrupts'\n", node);
-+ return -EINVAL;
-+ }
-+
-+ if (of_address_to_resource(node, 0, &res)) {
-+ pr_err("%pOF: DT: Failed to get 'reg'\n", node);
-+ ret = -EINVAL;
-+ goto err_dispose_mapping;
-+ }
-+
-+ if (!request_mem_region(res.start, resource_size(&res), res.name)) {
-+ pr_err("%pOF: Failed to request memory\n", node);
-+ ret = -EBUSY;
-+ goto err_dispose_mapping;
-+ }
-+
-+ econet_intc.membase = ioremap(res.start, resource_size(&res));
-+ if (!econet_intc.membase) {
-+ pr_err("%pOF: Failed to remap membase\n", node);
-+ ret = -ENOMEM;
-+ goto err_release;
-+ }
-+
-+ econet_mask_all();
-+
-+ domain = irq_domain_add_linear(node, IRQ_COUNT, &econet_domain_ops, NULL);
-+ if (!domain) {
-+ pr_err("%pOF: Failed to add irqdomain\n", node);
-+ ret = -ENOMEM;
-+ goto err_unmap;
-+ }
-+
-+ irq_set_chained_handler_and_data(irq, econet_intc_from_parent, domain);
-+
-+ return 0;
-+
-+err_unmap:
-+ iounmap(econet_intc.membase);
-+err_release:
-+ release_mem_region(res.start, resource_size(&res));
-+err_dispose_mapping:
-+ irq_dispose_mapping(irq);
-+ return ret;
-+}
-+
-+IRQCHIP_DECLARE(econet_en751221_intc, "econet,en751221-intc", econet_intc_of_init);
+++ /dev/null
-From 9e0dd98654a528735d2b363d0dc73f7904108652 Mon Sep 17 00:00:00 2001
-From: Caleb James DeLisle <cjd@cjdns.fr>
-Date: Sun, 30 Mar 2025 17:02:57 +0000
-Subject: [PATCH] dt-bindings: vendor-prefixes: Add EcoNet
-
-Add the "econet" vendor prefix for SoC maker
-
-Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20250330170306.2584136-2-cjd@cjdns.fr
-Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
----
- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
-+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
-@@ -420,6 +420,8 @@ patternProperties:
- description: EBV Elektronik
- "^eckelmann,.*":
- description: Eckelmann AG
-+ "^econet,.*":
-+ description: EcoNet (HK) Limited
- "^edgeble,.*":
- description: Edgeble AI Technologies Pvt. Ltd.
- "^edimax,.*":
+++ /dev/null
-From 30fddbd5325459102e448c9a26a1bc15ef563381 Mon Sep 17 00:00:00 2001
-From: Caleb James DeLisle <cjd@cjdns.fr>
-Date: Wed, 7 May 2025 13:44:54 +0000
-Subject: [PATCH] dt-bindings: timer: Add EcoNet EN751221 "HPT" CPU Timer
-
-Add device tree bindings for the so-called high-precision timer (HPT)
-in the EcoNet EN751221 SoC.
-
-Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20250507134500.390547-2-cjd@cjdns.fr
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- .../bindings/timer/econet,en751221-timer.yaml | 80 +++++++++++++++++++
- 1 file changed, 80 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
-@@ -0,0 +1,80 @@
-+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/timer/econet,en751221-timer.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: EcoNet EN751221 High Precision Timer (HPT)
-+
-+maintainers:
-+ - Caleb James DeLisle <cjd@cjdns.fr>
-+
-+description:
-+ The EcoNet High Precision Timer (HPT) is a timer peripheral found in various
-+ EcoNet SoCs, including the EN751221 and EN751627 families. It provides per-VPE
-+ count/compare registers and a per-CPU control register, with a single interrupt
-+ line using a percpu-devid interrupt mechanism.
-+
-+properties:
-+ compatible:
-+ oneOf:
-+ - const: econet,en751221-timer
-+ - items:
-+ - const: econet,en751627-timer
-+ - const: econet,en751221-timer
-+
-+ reg:
-+ minItems: 1
-+ maxItems: 2
-+
-+ interrupts:
-+ maxItems: 1
-+ description: A percpu-devid timer interrupt shared across CPUs.
-+
-+ clocks:
-+ maxItems: 1
-+
-+required:
-+ - compatible
-+ - reg
-+ - interrupts
-+ - clocks
-+
-+allOf:
-+ - if:
-+ properties:
-+ compatible:
-+ contains:
-+ const: econet,en751627-timer
-+ then:
-+ properties:
-+ reg:
-+ items:
-+ - description: VPE timers 0 and 1
-+ - description: VPE timers 2 and 3
-+ else:
-+ properties:
-+ reg:
-+ items:
-+ - description: VPE timers 0 and 1
-+
-+additionalProperties: false
-+
-+examples:
-+ - |
-+ timer@1fbf0400 {
-+ compatible = "econet,en751627-timer", "econet,en751221-timer";
-+ reg = <0x1fbf0400 0x100>, <0x1fbe0000 0x100>;
-+ interrupt-parent = <&intc>;
-+ interrupts = <30>;
-+ clocks = <&hpt_clock>;
-+ };
-+ - |
-+ timer@1fbf0400 {
-+ compatible = "econet,en751221-timer";
-+ reg = <0x1fbe0400 0x100>;
-+ interrupt-parent = <&intc>;
-+ interrupts = <30>;
-+ clocks = <&hpt_clock>;
-+ };
-+...
+++ /dev/null
-From 3b4c33ac87d0d11308f4445ecec2a124e2e77724 Mon Sep 17 00:00:00 2001
-From: Caleb James DeLisle <cjd@cjdns.fr>
-Date: Wed, 7 May 2025 13:44:55 +0000
-Subject: [PATCH] clocksource/drivers: Add EcoNet Timer HPT driver
-
-Introduce a clocksource driver for the so-called high-precision timer (HPT)
-in the EcoNet EN751221 and EN751627 MIPS SoCs.
-
-It's a 32 bit upward-counting one-shot timer which relies on the crystal so it
-is unaffected by CPU power mode. On MIPS 34K devices (single core) there is
-one timer, and on 1004K devices (dual core) there are two.
-
-Each timer has two sets of count/compare registers so that there is one for
-each of the VPEs on the core. Because each core has 2 VPEs, register selection
-takes the CPU number / 2 for the timer corrisponding to the core, then CPU
-number % 2 for the register corrisponding to the VPE.
-
-These timers use a percpu-devid IRQ to route interrupts to the VPE which set
-the event.
-
-Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
-Link: https://lore.kernel.org/r/20250507134500.390547-3-cjd@cjdns.fr
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/clocksource/Kconfig | 8 +
- drivers/clocksource/Makefile | 1 +
- drivers/clocksource/timer-econet-en751221.c | 216 ++++++++++++++++++++
- 3 files changed, 225 insertions(+)
- create mode 100644 drivers/clocksource/timer-econet-en751221.c
-
---- a/drivers/clocksource/Kconfig
-+++ b/drivers/clocksource/Kconfig
-@@ -73,6 +73,14 @@ config DW_APB_TIMER_OF
- select DW_APB_TIMER
- select TIMER_OF
-
-+config ECONET_EN751221_TIMER
-+ bool "EcoNet EN751221 High Precision Timer" if COMPILE_TEST
-+ depends on HAS_IOMEM
-+ select CLKSRC_MMIO
-+ select TIMER_OF
-+ help
-+ Support for CPU timer found on EcoNet MIPS based SoCs.
-+
- config FTTMR010_TIMER
- bool "Faraday Technology timer driver" if COMPILE_TEST
- depends on HAS_IOMEM
---- a/drivers/clocksource/Makefile
-+++ b/drivers/clocksource/Makefile
-@@ -17,6 +17,7 @@ obj-$(CONFIG_CLKBLD_I8253) += i8253.o
- obj-$(CONFIG_CLKSRC_MMIO) += mmio.o
- obj-$(CONFIG_DAVINCI_TIMER) += timer-davinci.o
- obj-$(CONFIG_DIGICOLOR_TIMER) += timer-digicolor.o
-+obj-$(CONFIG_ECONET_EN751221_TIMER) += timer-econet-en751221.o
- obj-$(CONFIG_OMAP_DM_TIMER) += timer-ti-dm.o
- obj-$(CONFIG_OMAP_DM_SYSTIMER) += timer-ti-dm-systimer.o
- obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o
---- /dev/null
-+++ b/drivers/clocksource/timer-econet-en751221.c
-@@ -0,0 +1,216 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Timer present on EcoNet EN75xx MIPS based SoCs.
-+ *
-+ * Copyright (C) 2025 by Caleb James DeLisle <cjd@cjdns.fr>
-+ */
-+
-+#include <linux/io.h>
-+#include <linux/cpumask.h>
-+#include <linux/interrupt.h>
-+#include <linux/clockchips.h>
-+#include <linux/sched_clock.h>
-+#include <linux/of.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_address.h>
-+#include <linux/cpuhotplug.h>
-+#include <linux/clk.h>
-+
-+#define ECONET_BITS 32
-+#define ECONET_MIN_DELTA 0x00001000
-+#define ECONET_MAX_DELTA GENMASK(ECONET_BITS - 2, 0)
-+/* 34Kc hardware has 1 block and 1004Kc has 2. */
-+#define ECONET_NUM_BLOCKS DIV_ROUND_UP(NR_CPUS, 2)
-+
-+static struct {
-+ void __iomem *membase[ECONET_NUM_BLOCKS];
-+ u32 freq_hz;
-+} econet_timer __ro_after_init;
-+
-+static DEFINE_PER_CPU(struct clock_event_device, econet_timer_pcpu);
-+
-+/* Each memory block has 2 timers, the order of registers is:
-+ * CTL, CMR0, CNT0, CMR1, CNT1
-+ */
-+static inline void __iomem *reg_ctl(u32 timer_n)
-+{
-+ return econet_timer.membase[timer_n >> 1];
-+}
-+
-+static inline void __iomem *reg_compare(u32 timer_n)
-+{
-+ return econet_timer.membase[timer_n >> 1] + (timer_n & 1) * 0x08 + 0x04;
-+}
-+
-+static inline void __iomem *reg_count(u32 timer_n)
-+{
-+ return econet_timer.membase[timer_n >> 1] + (timer_n & 1) * 0x08 + 0x08;
-+}
-+
-+static inline u32 ctl_bit_enabled(u32 timer_n)
-+{
-+ return 1U << (timer_n & 1);
-+}
-+
-+static inline u32 ctl_bit_pending(u32 timer_n)
-+{
-+ return 1U << ((timer_n & 1) + 16);
-+}
-+
-+static bool cevt_is_pending(int cpu_id)
-+{
-+ return ioread32(reg_ctl(cpu_id)) & ctl_bit_pending(cpu_id);
-+}
-+
-+static irqreturn_t cevt_interrupt(int irq, void *dev_id)
-+{
-+ struct clock_event_device *dev = this_cpu_ptr(&econet_timer_pcpu);
-+ int cpu = cpumask_first(dev->cpumask);
-+
-+ /* Each VPE has its own events,
-+ * so this will only happen on spurious interrupt.
-+ */
-+ if (!cevt_is_pending(cpu))
-+ return IRQ_NONE;
-+
-+ iowrite32(ioread32(reg_count(cpu)), reg_compare(cpu));
-+ dev->event_handler(dev);
-+ return IRQ_HANDLED;
-+}
-+
-+static int cevt_set_next_event(ulong delta, struct clock_event_device *dev)
-+{
-+ u32 next;
-+ int cpu;
-+
-+ cpu = cpumask_first(dev->cpumask);
-+ next = ioread32(reg_count(cpu)) + delta;
-+ iowrite32(next, reg_compare(cpu));
-+
-+ if ((s32)(next - ioread32(reg_count(cpu))) < ECONET_MIN_DELTA / 2)
-+ return -ETIME;
-+
-+ return 0;
-+}
-+
-+static int cevt_init_cpu(uint cpu)
-+{
-+ struct clock_event_device *cd = &per_cpu(econet_timer_pcpu, cpu);
-+ u32 reg;
-+
-+ pr_debug("%s: Setting up clockevent for CPU %d\n", cd->name, cpu);
-+
-+ reg = ioread32(reg_ctl(cpu)) | ctl_bit_enabled(cpu);
-+ iowrite32(reg, reg_ctl(cpu));
-+
-+ enable_percpu_irq(cd->irq, IRQ_TYPE_NONE);
-+
-+ /* Do this last because it synchronously configures the timer */
-+ clockevents_config_and_register(cd, econet_timer.freq_hz,
-+ ECONET_MIN_DELTA, ECONET_MAX_DELTA);
-+
-+ return 0;
-+}
-+
-+static u64 notrace sched_clock_read(void)
-+{
-+ /* Always read from clock zero no matter the CPU */
-+ return (u64)ioread32(reg_count(0));
-+}
-+
-+/* Init */
-+
-+static void __init cevt_dev_init(uint cpu)
-+{
-+ iowrite32(0, reg_count(cpu));
-+ iowrite32(U32_MAX, reg_compare(cpu));
-+}
-+
-+static int __init cevt_init(struct device_node *np)
-+{
-+ int i, irq, ret;
-+
-+ irq = irq_of_parse_and_map(np, 0);
-+ if (irq <= 0) {
-+ pr_err("%pOFn: irq_of_parse_and_map failed", np);
-+ return -EINVAL;
-+ }
-+
-+ ret = request_percpu_irq(irq, cevt_interrupt, np->name, &econet_timer_pcpu);
-+
-+ if (ret < 0) {
-+ pr_err("%pOFn: IRQ %d setup failed (%d)\n", np, irq, ret);
-+ goto err_unmap_irq;
-+ }
-+
-+ for_each_possible_cpu(i) {
-+ struct clock_event_device *cd = &per_cpu(econet_timer_pcpu, i);
-+
-+ cd->rating = 310,
-+ cd->features = CLOCK_EVT_FEAT_ONESHOT |
-+ CLOCK_EVT_FEAT_C3STOP |
-+ CLOCK_EVT_FEAT_PERCPU;
-+ cd->set_next_event = cevt_set_next_event;
-+ cd->irq = irq;
-+ cd->cpumask = cpumask_of(i);
-+ cd->name = np->name;
-+
-+ cevt_dev_init(i);
-+ }
-+
-+ cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
-+ "clockevents/econet/timer:starting",
-+ cevt_init_cpu, NULL);
-+ return 0;
-+
-+err_unmap_irq:
-+ irq_dispose_mapping(irq);
-+ return ret;
-+}
-+
-+static int __init timer_init(struct device_node *np)
-+{
-+ int num_blocks = DIV_ROUND_UP(num_possible_cpus(), 2);
-+ struct clk *clk;
-+ int ret;
-+
-+ clk = of_clk_get(np, 0);
-+ if (IS_ERR(clk)) {
-+ pr_err("%pOFn: Failed to get CPU clock from DT %ld\n", np, PTR_ERR(clk));
-+ return PTR_ERR(clk);
-+ }
-+
-+ econet_timer.freq_hz = clk_get_rate(clk);
-+
-+ for (int i = 0; i < num_blocks; i++) {
-+ econet_timer.membase[i] = of_iomap(np, i);
-+ if (!econet_timer.membase[i]) {
-+ pr_err("%pOFn: failed to map register [%d]\n", np, i);
-+ return -ENXIO;
-+ }
-+ }
-+
-+ /* For clocksource purposes always read clock zero, whatever the CPU */
-+ ret = clocksource_mmio_init(reg_count(0), np->name,
-+ econet_timer.freq_hz, 301, ECONET_BITS,
-+ clocksource_mmio_readl_up);
-+ if (ret) {
-+ pr_err("%pOFn: clocksource_mmio_init failed: %d", np, ret);
-+ return ret;
-+ }
-+
-+ ret = cevt_init(np);
-+ if (ret < 0)
-+ return ret;
-+
-+ sched_clock_register(sched_clock_read, ECONET_BITS,
-+ econet_timer.freq_hz);
-+
-+ pr_info("%pOFn: using %u.%03u MHz high precision timer\n", np,
-+ econet_timer.freq_hz / 1000000,
-+ (econet_timer.freq_hz / 1000) % 1000);
-+
-+ return 0;
-+}
-+
-+TIMER_OF_DECLARE(econet_timer_hpt, "econet,en751221-timer", timer_init);
+++ /dev/null
-From be8b4173719a61fdd8379e86895d855775cf5f91 Mon Sep 17 00:00:00 2001
-From: Caleb James DeLisle <cjd@cjdns.fr>
-Date: Wed, 7 May 2025 13:44:56 +0000
-Subject: [PATCH] dt-bindings: mips: Add EcoNet platform binding
-
-Document the top-level device tree binding for EcoNet MIPS-based SoCs.
-
-Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- .../devicetree/bindings/mips/econet.yaml | 26 +++++++++++++++++++
- 1 file changed, 26 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/mips/econet.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/mips/econet.yaml
-@@ -0,0 +1,26 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/mips/econet.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: EcoNet MIPS SoCs
-+
-+maintainers:
-+ - Caleb James DeLisle <cjd@cjdns.fr>
-+
-+properties:
-+ $nodename:
-+ const: '/'
-+
-+ compatible:
-+ oneOf:
-+ - description: Boards with EcoNet EN751221 family SoC
-+ items:
-+ - enum:
-+ - smartfiber,xp8421-b
-+ - const: econet,en751221
-+
-+additionalProperties: true
-+
-+...
+++ /dev/null
-From 35fb26f94dfa1b291086b84b2421f957214824d1 Mon Sep 17 00:00:00 2001
-From: Caleb James DeLisle <cjd@cjdns.fr>
-Date: Wed, 7 May 2025 13:44:57 +0000
-Subject: [PATCH] mips: Add EcoNet MIPS platform support
-
-Add platform support for EcoNet MIPS SoCs.
-
-Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/Kbuild.platforms | 1 +
- arch/mips/Kconfig | 25 +++++++++
- arch/mips/boot/compressed/uart-16550.c | 5 ++
- arch/mips/econet/Kconfig | 37 ++++++++++++
- arch/mips/econet/Makefile | 2 +
- arch/mips/econet/Platform | 5 ++
- arch/mips/econet/init.c | 78 ++++++++++++++++++++++++++
- 7 files changed, 153 insertions(+)
- create mode 100644 arch/mips/econet/Kconfig
- create mode 100644 arch/mips/econet/Makefile
- create mode 100644 arch/mips/econet/Platform
- create mode 100644 arch/mips/econet/init.c
-
---- a/arch/mips/Kbuild.platforms
-+++ b/arch/mips/Kbuild.platforms
-@@ -11,6 +11,7 @@ platform-$(CONFIG_CAVIUM_OCTEON_SOC) +=
- platform-$(CONFIG_EYEQ) += mobileye/
- platform-$(CONFIG_MIPS_COBALT) += cobalt/
- platform-$(CONFIG_MACH_DECSTATION) += dec/
-+platform-$(CONFIG_ECONET) += econet/
- platform-$(CONFIG_MIPS_GENERIC) += generic/
- platform-$(CONFIG_MACH_JAZZ) += jazz/
- platform-$(CONFIG_LANTIQ) += lantiq/
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -388,6 +388,30 @@ config MACH_DECSTATION
-
- otherwise choose R3000.
-
-+config ECONET
-+ bool "EcoNet MIPS family"
-+ select BOOT_RAW
-+ select CPU_BIG_ENDIAN
-+ select DEBUG_ZBOOT
-+ select EARLY_PRINTK_8250
-+ select ECONET_EN751221_TIMER
-+ select SERIAL_OF_PLATFORM
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_HAS_CPU_MIPS32_R1
-+ select SYS_HAS_CPU_MIPS32_R2
-+ select SYS_HAS_EARLY_PRINTK
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_MIPS16
-+ select SYS_SUPPORTS_ZBOOT_UART16550
-+ select USE_GENERIC_EARLY_PRINTK_8250
-+ select USE_OF
-+ help
-+ EcoNet EN75xx MIPS devices are big endian MIPS machines used
-+ in XPON (fiber) and DSL applications. They have SPI, PCI, USB,
-+ GPIO, and Ethernet, with optional XPON, DSL, and VoIP DSP cores.
-+ Don't confuse these with the Airoha ARM devices sometimes referred
-+ to as "EcoNet", this family is for MIPS based devices only.
-+
- config MACH_JAZZ
- bool "Jazz family of machines"
- select ARC_MEMORY
-@@ -1017,6 +1041,7 @@ source "arch/mips/ath79/Kconfig"
- source "arch/mips/bcm47xx/Kconfig"
- source "arch/mips/bcm63xx/Kconfig"
- source "arch/mips/bmips/Kconfig"
-+source "arch/mips/econet/Kconfig"
- source "arch/mips/generic/Kconfig"
- source "arch/mips/ingenic/Kconfig"
- source "arch/mips/jazz/Kconfig"
---- a/arch/mips/boot/compressed/uart-16550.c
-+++ b/arch/mips/boot/compressed/uart-16550.c
-@@ -20,6 +20,11 @@
- #define PORT(offset) (CKSEG1ADDR(INGENIC_UART_BASE_ADDR) + (4 * offset))
- #endif
-
-+#ifdef CONFIG_ECONET
-+#define EN75_UART_BASE 0x1fbf0003
-+#define PORT(offset) (CKSEG1ADDR(EN75_UART_BASE) + (4 * (offset)))
-+#endif
-+
- #ifndef IOTYPE
- #define IOTYPE char
- #endif
---- /dev/null
-+++ b/arch/mips/econet/Kconfig
-@@ -0,0 +1,37 @@
-+# SPDX-License-Identifier: GPL-2.0
-+if ECONET
-+
-+choice
-+ prompt "EcoNet SoC selection"
-+ default SOC_ECONET_EN751221
-+ help
-+ Select EcoNet MIPS SoC type. Individual SoCs within a family are
-+ very similar, so is it enough to select the right family, and
-+ then customize to the specific SoC using the device tree only.
-+
-+ config SOC_ECONET_EN751221
-+ bool "EN751221 family"
-+ select COMMON_CLK
-+ select ECONET_EN751221_INTC
-+ select IRQ_MIPS_CPU
-+ select SMP
-+ select SMP_UP
-+ select SYS_SUPPORTS_SMP
-+ help
-+ The EN751221 family includes EN7512, RN7513, EN7521, EN7526.
-+ They are based on single core MIPS 34Kc processors. To boot
-+ this kernel, you will need a device tree such as
-+ MIPS_RAW_APPENDED_DTB=y, and a root filesystem.
-+endchoice
-+
-+choice
-+ prompt "Devicetree selection"
-+ default DTB_ECONET_NONE
-+ help
-+ Select the devicetree.
-+
-+ config DTB_ECONET_NONE
-+ bool "None"
-+endchoice
-+
-+endif
---- /dev/null
-+++ b/arch/mips/econet/Makefile
-@@ -0,0 +1,2 @@
-+
-+obj-y := init.o
---- /dev/null
-+++ b/arch/mips/econet/Platform
-@@ -0,0 +1,5 @@
-+# To address a 7.2MB kernel size limit in the EcoNet SDK bootloader,
-+# we put the load address well above where the bootloader loads and then use
-+# zboot. So please set CONFIG_ZBOOT_LOAD_ADDRESS to the address where your
-+# bootloader actually places the kernel.
-+load-$(CONFIG_ECONET) += 0xffffffff81000000
---- /dev/null
-+++ b/arch/mips/econet/init.c
-@@ -0,0 +1,78 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * EcoNet setup code
-+ *
-+ * Copyright (C) 2025 Caleb James DeLisle <cjd@cjdns.fr>
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/of_clk.h>
-+#include <linux/irqchip.h>
-+
-+#include <asm/addrspace.h>
-+#include <asm/io.h>
-+#include <asm/bootinfo.h>
-+#include <asm/time.h>
-+#include <asm/prom.h>
-+#include <asm/smp-ops.h>
-+#include <asm/reboot.h>
-+
-+#define CR_AHB_RSTCR ((void __iomem *)CKSEG1ADDR(0x1fb00040))
-+#define RESET BIT(31)
-+
-+#define UART_BASE CKSEG1ADDR(0x1fbf0003)
-+#define UART_REG_SHIFT 2
-+
-+static void hw_reset(char *command)
-+{
-+ iowrite32(RESET, CR_AHB_RSTCR);
-+}
-+
-+/* 1. Bring up early printk. */
-+void __init prom_init(void)
-+{
-+ setup_8250_early_printk_port(UART_BASE, UART_REG_SHIFT, 0);
-+ _machine_restart = hw_reset;
-+}
-+
-+/* 2. Parse the DT and find memory */
-+void __init plat_mem_setup(void)
-+{
-+ void *dtb;
-+
-+ set_io_port_base(KSEG1);
-+
-+ dtb = get_fdt();
-+ if (!dtb)
-+ panic("no dtb found");
-+
-+ __dt_setup_arch(dtb);
-+
-+ early_init_dt_scan_memory();
-+}
-+
-+/* 3. Overload __weak device_tree_init(), add SMP_UP ops */
-+void __init device_tree_init(void)
-+{
-+ unflatten_and_copy_device_tree();
-+
-+ register_up_smp_ops();
-+}
-+
-+const char *get_system_type(void)
-+{
-+ return "EcoNet-EN75xx";
-+}
-+
-+/* 4. Initialize the IRQ subsystem */
-+void __init arch_init_irq(void)
-+{
-+ irqchip_init();
-+}
-+
-+/* 5. Timers */
-+void __init plat_time_init(void)
-+{
-+ of_clk_init(NULL);
-+ timer_probe();
-+}
+++ /dev/null
-From abc2d0bc2cb7c1412b8b254c0446f94b3e203c7c Mon Sep 17 00:00:00 2001
-From: Caleb James DeLisle <cjd@cjdns.fr>
-Date: Wed, 7 May 2025 13:44:58 +0000
-Subject: [PATCH] dt-bindings: vendor-prefixes: Add SmartFiber
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add "smartfiber" vendor prefix for manufactorer of EcoNet based boards.
-
-Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
-+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
-@@ -1370,6 +1370,8 @@ patternProperties:
- description: SKOV A/S
- "^skyworks,.*":
- description: Skyworks Solutions, Inc.
-+ "^smartfiber,.*":
-+ description: ShenZhen Smartfiber Technology Co, Ltd.
- "^smartlabs,.*":
- description: SmartLabs LLC
- "^smartrg,.*":
+++ /dev/null
-From 0ec4887009729297f7c10368084e41a8a9fbbd0e Mon Sep 17 00:00:00 2001
-From: Caleb James DeLisle <cjd@cjdns.fr>
-Date: Wed, 7 May 2025 13:44:59 +0000
-Subject: [PATCH] mips: dts: Add EcoNet DTS with EN751221 and SmartFiber
- XP8421-B board
-
-Add DTS files in support of EcoNet platform, including SmartFiber XP8421-B,
-a low cost commercially available board based on EN751221.
-
-Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/boot/dts/Makefile | 1 +
- arch/mips/boot/dts/econet/Makefile | 2 +
- arch/mips/boot/dts/econet/en751221.dtsi | 67 +++++++++++++++++++
- .../econet/en751221_smartfiber_xp8421-b.dts | 19 ++++++
- arch/mips/econet/Kconfig | 11 +++
- 5 files changed, 100 insertions(+)
- create mode 100644 arch/mips/boot/dts/econet/Makefile
- create mode 100644 arch/mips/boot/dts/econet/en751221.dtsi
- create mode 100644 arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts
-
---- a/arch/mips/boot/dts/Makefile
-+++ b/arch/mips/boot/dts/Makefile
-@@ -1,6 +1,7 @@
- # SPDX-License-Identifier: GPL-2.0
- subdir-$(CONFIG_BMIPS_GENERIC) += brcm
- subdir-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon
-+subdir-$(CONFIG_ECONET) += econet
- subdir-$(CONFIG_EYEQ) += mobileye
- subdir-$(CONFIG_FIT_IMAGE_FDT_MARDUK) += img
- subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += img
---- /dev/null
-+++ b/arch/mips/boot/dts/econet/Makefile
-@@ -0,0 +1,2 @@
-+# SPDX-License-Identifier: GPL-2.0
-+dtb-$(CONFIG_DTB_ECONET_SMARTFIBER_XP8421_B) += en751221_smartfiber_xp8421-b.dtb
---- /dev/null
-+++ b/arch/mips/boot/dts/econet/en751221.dtsi
-@@ -0,0 +1,67 @@
-+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+/dts-v1/;
-+
-+/ {
-+ compatible = "econet,en751221";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ hpt_clock: clock {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <200000000>; /* 200 MHz */
-+ };
-+
-+ cpus: cpus {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ cpu@0 {
-+ device_type = "cpu";
-+ compatible = "mips,mips24KEc";
-+ reg = <0>;
-+ };
-+ };
-+
-+ cpuintc: interrupt-controller {
-+ compatible = "mti,cpu-interrupt-controller";
-+ interrupt-controller;
-+ #address-cells = <0>;
-+ #interrupt-cells = <1>;
-+ };
-+
-+ intc: interrupt-controller@1fb40000 {
-+ compatible = "econet,en751221-intc";
-+ reg = <0x1fb40000 0x100>;
-+ interrupt-parent = <&cpuintc>;
-+ interrupts = <2>;
-+
-+ interrupt-controller;
-+ #interrupt-cells = <1>;
-+ econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;
-+ };
-+
-+ uart: serial@1fbf0000 {
-+ compatible = "ns16550";
-+ reg = <0x1fbf0000 0x30>;
-+ reg-io-width = <4>;
-+ reg-shift = <2>;
-+ interrupt-parent = <&intc>;
-+ interrupts = <0>;
-+ /*
-+ * Conversion of baud rate to clock frequency requires a
-+ * computation that is not in the ns16550 driver, so this
-+ * uart is fixed at 115200 baud.
-+ */
-+ clock-frequency = <1843200>;
-+ };
-+
-+ timer_hpt: timer@1fbf0400 {
-+ compatible = "econet,en751221-timer";
-+ reg = <0x1fbf0400 0x100>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <30>;
-+ clocks = <&hpt_clock>;
-+ };
-+};
---- /dev/null
-+++ b/arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts
-@@ -0,0 +1,19 @@
-+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+/dts-v1/;
-+
-+#include "en751221.dtsi"
-+
-+/ {
-+ model = "SmartFiber XP8421-B";
-+ compatible = "smartfiber,xp8421-b", "econet,en751221";
-+
-+ memory@0 {
-+ device_type = "memory";
-+ reg = <0x00000000 0x1c000000>;
-+ };
-+
-+ chosen {
-+ stdout-path = "/serial@1fbf0000:115200";
-+ linux,usable-memory-range = <0x00020000 0x1bfe0000>;
-+ };
-+};
---- a/arch/mips/econet/Kconfig
-+++ b/arch/mips/econet/Kconfig
-@@ -32,6 +32,17 @@ choice
-
- config DTB_ECONET_NONE
- bool "None"
-+
-+ config DTB_ECONET_SMARTFIBER_XP8421_B
-+ bool "EN751221 SmartFiber XP8421-B"
-+ depends on SOC_ECONET_EN751221
-+ select BUILTIN_DTB
-+ help
-+ The SmartFiber XP8421-B is a device based on the EN751221 SoC.
-+ It has 512MB of memory and 256MB of NAND flash. This kernel
-+ needs only an appended initramfs to boot. It can be loaded
-+ through XMODEM and booted from memory in the bootloader, or
-+ it can be packed in tclinux.trx format and written to flash.
- endchoice
-
- endif
+++ /dev/null
-From faefb0a59c5914b7b8f737e2ec5c82822e5bc4c7 Mon Sep 17 00:00:00 2001
-From: Caleb James DeLisle <cjd@cjdns.fr>
-Date: Wed, 7 May 2025 13:45:00 +0000
-Subject: [PATCH] MAINTAINERS: Add entry for newly added EcoNet platform.
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add a MAINTAINERS entry as part of integration of the EcoNet MIPS platform.
-
-Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- MAINTAINERS | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -8025,6 +8025,18 @@ W: https://linuxtv.org
- Q: http://patchwork.linuxtv.org/project/linux-media/list/
- F: drivers/media/dvb-frontends/ec100*
-
-+ECONET MIPS PLATFORM
-+M: Caleb James DeLisle <cjd@cjdns.fr>
-+L: linux-mips@vger.kernel.org
-+S: Maintained
-+F: Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml
-+F: Documentation/devicetree/bindings/mips/econet.yaml
-+F: Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
-+F: arch/mips/boot/dts/econet/
-+F: arch/mips/econet/
-+F: drivers/clocksource/timer-econet-en751221.c
-+F: drivers/irqchip/irq-econet-en751221.c
-+
- ECRYPT FILE SYSTEM
- M: Tyler Hicks <code@tyhicks.com>
- L: ecryptfs@vger.kernel.org
+++ /dev/null
-From 79ee1d20e37cd553cc961962fca8107e69a0c293 Mon Sep 17 00:00:00 2001
-From: Caleb James DeLisle <cjd@cjdns.fr>
-Date: Wed, 21 May 2025 21:33:33 +0000
-Subject: [PATCH] mips: econet: Fix incorrect Kconfig dependencies
-
-config ECONET selects SERIAL_OF_PLATFORM and that depends on SERIAL_8250
-so we need to select SERIAL_8250 directly.
-Also do not enable DEBUG_ZBOOT unless DEBUG_KERNEL is set.
-
-Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
-Reported-by: kernel test robot <lkp@intel.com>
-Closes: https://lore.kernel.org/oe-kbuild-all/202505211654.CBdIsoTq-lkp@intel.com/
-Closes: https://lore.kernel.org/oe-kbuild-all/202505211451.WRjyf3a9-lkp@intel.com/
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/Kconfig | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -392,9 +392,10 @@ config ECONET
- bool "EcoNet MIPS family"
- select BOOT_RAW
- select CPU_BIG_ENDIAN
-- select DEBUG_ZBOOT
-+ select DEBUG_ZBOOT if DEBUG_KERNEL
- select EARLY_PRINTK_8250
- select ECONET_EN751221_TIMER
-+ select SERIAL_8250
- select SERIAL_OF_PLATFORM
- select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_HAS_CPU_MIPS32_R1
+++ /dev/null
-From 82e6bf912d5846646892becea659b39d178d79e3 Mon Sep 17 00:00:00 2001
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Tue, 12 Nov 2024 01:08:53 +0100
-Subject: [PATCH 5/8] clk: en7523: move en7581_reset_register() in
- en7581_clk_hw_init()
-
-Move en7581_reset_register routine in en7581_clk_hw_init() since reset
-feature is supported just by EN7581 SoC.
-Get rid of reset struct in en_clk_soc_data data struct.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Link: https://lore.kernel.org/r/20241112-clk-en7581-syscon-v2-6-8ada5e394ae4@kernel.org
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/clk-en7523.c | 93 ++++++++++++++--------------------------
- 1 file changed, 33 insertions(+), 60 deletions(-)
-
---- a/drivers/clk/clk-en7523.c
-+++ b/drivers/clk/clk-en7523.c
-@@ -76,11 +76,6 @@ struct en_rst_data {
-
- struct en_clk_soc_data {
- const struct clk_ops pcie_ops;
-- struct {
-- const u16 *bank_ofs;
-- const u16 *idx_map;
-- u16 idx_map_nr;
-- } reset;
- int (*hw_init)(struct platform_device *pdev,
- struct clk_hw_onecell_data *clk_data);
- };
-@@ -596,32 +591,6 @@ static void en7581_register_clocks(struc
- clk_data->num = EN7523_NUM_CLOCKS;
- }
-
--static int en7581_clk_hw_init(struct platform_device *pdev,
-- struct clk_hw_onecell_data *clk_data)
--{
-- void __iomem *np_base;
-- struct regmap *map;
-- u32 val;
--
-- map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu");
-- if (IS_ERR(map))
-- return PTR_ERR(map);
--
-- np_base = devm_platform_ioremap_resource(pdev, 0);
-- if (IS_ERR(np_base))
-- return PTR_ERR(np_base);
--
-- en7581_register_clocks(&pdev->dev, clk_data, map, np_base);
--
-- val = readl(np_base + REG_NP_SCU_SSTR);
-- val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
-- writel(val, np_base + REG_NP_SCU_SSTR);
-- val = readl(np_base + REG_NP_SCU_PCIC);
-- writel(val | 3, np_base + REG_NP_SCU_PCIC);
--
-- return 0;
--}
--
- static int en7523_reset_update(struct reset_controller_dev *rcdev,
- unsigned long id, bool assert)
- {
-@@ -671,23 +640,18 @@ static int en7523_reset_xlate(struct res
- return rst_data->idx_map[reset_spec->args[0]];
- }
-
--static const struct reset_control_ops en7523_reset_ops = {
-+static const struct reset_control_ops en7581_reset_ops = {
- .assert = en7523_reset_assert,
- .deassert = en7523_reset_deassert,
- .status = en7523_reset_status,
- };
-
--static int en7523_reset_register(struct platform_device *pdev,
-- const struct en_clk_soc_data *soc_data)
-+static int en7581_reset_register(struct platform_device *pdev)
- {
- struct device *dev = &pdev->dev;
- struct en_rst_data *rst_data;
- void __iomem *base;
-
-- /* no reset lines available */
-- if (!soc_data->reset.idx_map_nr)
-- return 0;
--
- base = devm_platform_ioremap_resource(pdev, 1);
- if (IS_ERR(base))
- return PTR_ERR(base);
-@@ -696,13 +660,13 @@ static int en7523_reset_register(struct
- if (!rst_data)
- return -ENOMEM;
-
-- rst_data->bank_ofs = soc_data->reset.bank_ofs;
-- rst_data->idx_map = soc_data->reset.idx_map;
-+ rst_data->bank_ofs = en7581_rst_ofs;
-+ rst_data->idx_map = en7581_rst_map;
- rst_data->base = base;
-
-- rst_data->rcdev.nr_resets = soc_data->reset.idx_map_nr;
-+ rst_data->rcdev.nr_resets = ARRAY_SIZE(en7581_rst_map);
- rst_data->rcdev.of_xlate = en7523_reset_xlate;
-- rst_data->rcdev.ops = &en7523_reset_ops;
-+ rst_data->rcdev.ops = &en7581_reset_ops;
- rst_data->rcdev.of_node = dev->of_node;
- rst_data->rcdev.of_reset_n_cells = 1;
- rst_data->rcdev.owner = THIS_MODULE;
-@@ -711,6 +675,32 @@ static int en7523_reset_register(struct
- return devm_reset_controller_register(dev, &rst_data->rcdev);
- }
-
-+static int en7581_clk_hw_init(struct platform_device *pdev,
-+ struct clk_hw_onecell_data *clk_data)
-+{
-+ void __iomem *np_base;
-+ struct regmap *map;
-+ u32 val;
-+
-+ map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu");
-+ if (IS_ERR(map))
-+ return PTR_ERR(map);
-+
-+ np_base = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(np_base))
-+ return PTR_ERR(np_base);
-+
-+ en7581_register_clocks(&pdev->dev, clk_data, map, np_base);
-+
-+ val = readl(np_base + REG_NP_SCU_SSTR);
-+ val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
-+ writel(val, np_base + REG_NP_SCU_SSTR);
-+ val = readl(np_base + REG_NP_SCU_PCIC);
-+ writel(val | 3, np_base + REG_NP_SCU_PCIC);
-+
-+ return en7581_reset_register(pdev);
-+}
-+
- static int en7523_clk_probe(struct platform_device *pdev)
- {
- struct device_node *node = pdev->dev.of_node;
-@@ -729,19 +719,7 @@ static int en7523_clk_probe(struct platf
- if (r)
- return r;
-
-- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-- if (r)
-- return dev_err_probe(&pdev->dev, r, "Could not register clock provider: %s\n",
-- pdev->name);
--
-- r = en7523_reset_register(pdev, soc_data);
-- if (r) {
-- of_clk_del_provider(node);
-- return dev_err_probe(&pdev->dev, r, "Could not register reset controller: %s\n",
-- pdev->name);
-- }
--
-- return 0;
-+ return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- }
-
- static const struct en_clk_soc_data en7523_data = {
-@@ -759,11 +737,6 @@ static const struct en_clk_soc_data en75
- .enable = en7581_pci_enable,
- .disable = en7581_pci_disable,
- },
-- .reset = {
-- .bank_ofs = en7581_rst_ofs,
-- .idx_map = en7581_rst_map,
-- .idx_map_nr = ARRAY_SIZE(en7581_rst_map),
-- },
- .hw_init = en7581_clk_hw_init,
- };
-
+++ /dev/null
-From a9eaf305017a5ebe73ab34e85bd5414055a88f29 Mon Sep 17 00:00:00 2001
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Tue, 12 Nov 2024 01:08:54 +0100
-Subject: [PATCH 6/8] clk: en7523: map io region in a single block
-
-Map all clock-controller memory region in a single block.
-This patch does not introduce any backward incompatibility since the dts
-for EN7581 SoC is not upstream yet.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Link: https://lore.kernel.org/r/20241112-clk-en7581-syscon-v2-7-8ada5e394ae4@kernel.org
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/clk-en7523.c | 32 +++++++++++++-------------------
- 1 file changed, 13 insertions(+), 19 deletions(-)
-
---- a/drivers/clk/clk-en7523.c
-+++ b/drivers/clk/clk-en7523.c
-@@ -39,8 +39,8 @@
- #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
- #define REG_CRYPTO_CLKSRC2 0x20c
-
--#define REG_RST_CTRL2 0x00
--#define REG_RST_CTRL1 0x04
-+#define REG_RST_CTRL2 0x830
-+#define REG_RST_CTRL1 0x834
-
- struct en_clk_desc {
- int id;
-@@ -646,15 +646,9 @@ static const struct reset_control_ops en
- .status = en7523_reset_status,
- };
-
--static int en7581_reset_register(struct platform_device *pdev)
-+static int en7581_reset_register(struct device *dev, void __iomem *base)
- {
-- struct device *dev = &pdev->dev;
- struct en_rst_data *rst_data;
-- void __iomem *base;
--
-- base = devm_platform_ioremap_resource(pdev, 1);
-- if (IS_ERR(base))
-- return PTR_ERR(base);
-
- rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
- if (!rst_data)
-@@ -678,27 +672,27 @@ static int en7581_reset_register(struct
- static int en7581_clk_hw_init(struct platform_device *pdev,
- struct clk_hw_onecell_data *clk_data)
- {
-- void __iomem *np_base;
- struct regmap *map;
-+ void __iomem *base;
- u32 val;
-
- map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu");
- if (IS_ERR(map))
- return PTR_ERR(map);
-
-- np_base = devm_platform_ioremap_resource(pdev, 0);
-- if (IS_ERR(np_base))
-- return PTR_ERR(np_base);
-+ base = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(base))
-+ return PTR_ERR(base);
-
-- en7581_register_clocks(&pdev->dev, clk_data, map, np_base);
-+ en7581_register_clocks(&pdev->dev, clk_data, map, base);
-
-- val = readl(np_base + REG_NP_SCU_SSTR);
-+ val = readl(base + REG_NP_SCU_SSTR);
- val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
-- writel(val, np_base + REG_NP_SCU_SSTR);
-- val = readl(np_base + REG_NP_SCU_PCIC);
-- writel(val | 3, np_base + REG_NP_SCU_PCIC);
-+ writel(val, base + REG_NP_SCU_SSTR);
-+ val = readl(base + REG_NP_SCU_PCIC);
-+ writel(val | 3, base + REG_NP_SCU_PCIC);
-
-- return en7581_reset_register(pdev);
-+ return en7581_reset_register(&pdev->dev, base);
- }
-
- static int en7523_clk_probe(struct platform_device *pdev)
+++ /dev/null
-From 90d4e466c9ea2010f33880a36317a8486ccbe082 Mon Sep 17 00:00:00 2001
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Wed, 8 Jan 2025 10:50:43 +0100
-Subject: [PATCH 1/3] PCI: mediatek-gen3: Move reset delay in
- mtk_pcie_en7581_power_up()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal
-causing occasional PCIe link down issues. In order to overcome the
-problem, PCIe block is reset using REG_PCI_CONTROL (0x88) and
-REG_RESET_CONTROL (0x834) registers available in the clock module
-running clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up().
-
-In order to make the code more readable, move the wait for the time
-needed to complete the PCIe reset from en7581_pci_enable() to
-mtk_pcie_en7581_power_up().
-
-Reduce reset timeout from 250ms to the standard PCIE_T_PVPERL_MS value
-(100ms) since it has no impact on the driver behavior.
-
-Link: https://lore.kernel.org/r/20250108-pcie-en7581-fixes-v6-4-21ac939a3b9b@kernel.org
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-Acked-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/clk-en7523.c | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/drivers/clk/clk-en7523.c
-+++ b/drivers/clk/clk-en7523.c
-@@ -478,7 +478,6 @@ static int en7581_pci_enable(struct clk_
- REG_PCI_CONTROL_PERSTOUT;
- val = readl(np_base + REG_PCI_CONTROL);
- writel(val | mask, np_base + REG_PCI_CONTROL);
-- msleep(250);
-
- return 0;
- }
+++ /dev/null
-From e4a9748e7103c47e575459db2b6a77d14f34da2b Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 14 Jan 2025 00:10:02 +0100
-Subject: [PATCH 2/3] clk: en7523: Rework clock handling for different clock
- numbers
-
-Airoha EN7581 SoC have additional clock compared to EN7523 but current
-driver permits to only support up to EN7523 clock numbers.
-
-To handle this, rework the clock handling and permit to declare the
-clocks number in match_data and alloca clk_data based on the compatible
-match_data.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Link: https://lore.kernel.org/r/20250113231030.6735-2-ansuelsmth@gmail.com
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/clk-en7523.c | 14 ++++++++------
- 1 file changed, 8 insertions(+), 6 deletions(-)
-
---- a/drivers/clk/clk-en7523.c
-+++ b/drivers/clk/clk-en7523.c
-@@ -75,6 +75,7 @@ struct en_rst_data {
- };
-
- struct en_clk_soc_data {
-+ u32 num_clocks;
- const struct clk_ops pcie_ops;
- int (*hw_init)(struct platform_device *pdev,
- struct clk_hw_onecell_data *clk_data);
-@@ -503,8 +504,6 @@ static void en7523_register_clocks(struc
- u32 rate;
- int i;
-
-- clk_data->num = EN7523_NUM_CLOCKS;
--
- for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) {
- const struct en_clk_desc *desc = &en7523_base_clks[i];
- u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg;
-@@ -586,8 +585,6 @@ static void en7581_register_clocks(struc
-
- hw = en7523_register_pcie_clk(dev, base);
- clk_data->hws[EN7523_CLK_PCIE] = hw;
--
-- clk_data->num = EN7523_NUM_CLOCKS;
- }
-
- static int en7523_reset_update(struct reset_controller_dev *rcdev,
-@@ -701,13 +698,15 @@ static int en7523_clk_probe(struct platf
- struct clk_hw_onecell_data *clk_data;
- int r;
-
-+ soc_data = device_get_match_data(&pdev->dev);
-+
- clk_data = devm_kzalloc(&pdev->dev,
-- struct_size(clk_data, hws, EN7523_NUM_CLOCKS),
-+ struct_size(clk_data, hws, soc_data->num_clocks),
- GFP_KERNEL);
- if (!clk_data)
- return -ENOMEM;
-
-- soc_data = device_get_match_data(&pdev->dev);
-+ clk_data->num = soc_data->num_clocks;
- r = soc_data->hw_init(pdev, clk_data);
- if (r)
- return r;
-@@ -716,6 +715,7 @@ static int en7523_clk_probe(struct platf
- }
-
- static const struct en_clk_soc_data en7523_data = {
-+ .num_clocks = ARRAY_SIZE(en7523_base_clks) + 1,
- .pcie_ops = {
- .is_enabled = en7523_pci_is_enabled,
- .prepare = en7523_pci_prepare,
-@@ -725,6 +725,8 @@ static const struct en_clk_soc_data en75
- };
-
- static const struct en_clk_soc_data en7581_data = {
-+ /* We increment num_clocks by 1 to account for additional PCIe clock */
-+ .num_clocks = ARRAY_SIZE(en7581_base_clks) + 1,
- .pcie_ops = {
- .is_enabled = en7581_pci_is_enabled,
- .enable = en7581_pci_enable,
+++ /dev/null
-From bfe257f9780d8f77045a7da6ec959ee0659d2f98 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 14 Jan 2025 00:10:05 +0100
-Subject: [PATCH 3/3] clk: en7523: Add clock for eMMC for EN7581
-
-Add clock for eMMC for EN7581. This is used to give info of the current
-eMMC source clock and to switch it from 200MHz or 150MHz.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Link: https://lore.kernel.org/r/20250113231030.6735-5-ansuelsmth@gmail.com
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/clk-en7523.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/drivers/clk/clk-en7523.c
-+++ b/drivers/clk/clk-en7523.c
-@@ -91,6 +91,7 @@ static const u32 emi7581_base[] = { 5400
- static const u32 bus7581_base[] = { 600000000, 540000000 };
- static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
- static const u32 crypto_base[] = { 540000000, 480000000 };
-+static const u32 emmc7581_base[] = { 200000000, 150000000 };
-
- static const struct en_clk_desc en7523_base_clks[] = {
- {
-@@ -281,6 +282,15 @@ static const struct en_clk_desc en7581_b
- .base_shift = 0,
- .base_values = crypto_base,
- .n_base_values = ARRAY_SIZE(crypto_base),
-+ }, {
-+ .id = EN7581_CLK_EMMC,
-+ .name = "emmc",
-+
-+ .base_reg = REG_CRYPTO_CLKSRC2,
-+ .base_bits = 1,
-+ .base_shift = 12,
-+ .base_values = emmc7581_base,
-+ .n_base_values = ARRAY_SIZE(emmc7581_base),
- }
- };
-
+++ /dev/null
-From 0f7c637d1103d79829dec198e5f1b678c1feb5f2 Mon Sep 17 00:00:00 2001
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Tue, 12 Nov 2024 01:08:48 +0100
-Subject: [PATCH] dt-bindings: clock: airoha: Update reg mapping for EN7581
- SoC.
-
-clk-en7523 driver for EN7581 SoC is mapping all the scu memory region
-while it is configuring the chip-scu one via a syscon. Update the reg
-mapping definition for this device. This patch does not introduce any
-backward incompatibility since the dts for EN7581 SoC is not upstream
-yet.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Link: https://lore.kernel.org/r/20241112-clk-en7581-syscon-v2-1-8ada5e394ae4@kernel.org
-Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- .../bindings/clock/airoha,en7523-scu.yaml | 23 +++++++------------
- 1 file changed, 8 insertions(+), 15 deletions(-)
-
---- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
-+++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
-@@ -34,8 +34,10 @@ properties:
- - airoha,en7581-scu
-
- reg:
-- minItems: 2
-- maxItems: 4
-+ items:
-+ - description: scu base address
-+ - description: misc scu base address
-+ minItems: 1
-
- "#clock-cells":
- description:
-@@ -60,9 +62,7 @@ allOf:
- then:
- properties:
- reg:
-- items:
-- - description: scu base address
-- - description: misc scu base address
-+ minItems: 2
-
- - if:
- properties:
-@@ -71,11 +71,7 @@ allOf:
- then:
- properties:
- reg:
-- items:
-- - description: scu base address
-- - description: misc scu base address
-- - description: reset base address
-- - description: pb scu base address
-+ maxItems: 1
-
- additionalProperties: false
-
-@@ -95,12 +91,9 @@ examples:
- #address-cells = <2>;
- #size-cells = <2>;
-
-- scuclk: clock-controller@1fa20000 {
-+ scuclk: clock-controller@1fb00000 {
- compatible = "airoha,en7581-scu";
-- reg = <0x0 0x1fa20000 0x0 0x400>,
-- <0x0 0x1fb00000 0x0 0x90>,
-- <0x0 0x1fb00830 0x0 0x8>,
-- <0x0 0x1fbe3400 0x0 0xfc>;
-+ reg = <0x0 0x1fb00000 0x0 0x970>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
+++ /dev/null
-From 02d3b7557ce28c373ea1e925ae16ab5988284313 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 14 Jan 2025 00:10:03 +0100
-Subject: [PATCH 1/2] dt-bindings: clock: drop NUM_CLOCKS define for EN7581
-
-Drop NUM_CLOCKS define for EN7581 include. This is not a binding and
-should not be placed here. Value is derived internally in the user
-driver.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20250113231030.6735-3-ansuelsmth@gmail.com
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- include/dt-bindings/clock/en7523-clk.h | 2 --
- 1 file changed, 2 deletions(-)
-
---- a/include/dt-bindings/clock/en7523-clk.h
-+++ b/include/dt-bindings/clock/en7523-clk.h
-@@ -12,6 +12,4 @@
- #define EN7523_CLK_CRYPTO 6
- #define EN7523_CLK_PCIE 7
-
--#define EN7523_NUM_CLOCKS 8
--
- #endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */
+++ /dev/null
-From 82108ad3285f58f314ad41398f44017c7dbe44de Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 14 Jan 2025 00:10:04 +0100
-Subject: [PATCH 2/2] dt-bindings: clock: add ID for eMMC for EN7581
-
-Add ID for eMMC for EN7581. This is to control clock selection of eMMC
-between 200MHz and 150MHz.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Acked-by: Conor Dooley <conor.dooley@microchip.com>
-Link: https://lore.kernel.org/r/20250113231030.6735-4-ansuelsmth@gmail.com
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- include/dt-bindings/clock/en7523-clk.h | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/include/dt-bindings/clock/en7523-clk.h
-+++ b/include/dt-bindings/clock/en7523-clk.h
-@@ -12,4 +12,6 @@
- #define EN7523_CLK_CRYPTO 6
- #define EN7523_CLK_PCIE 7
-
-+#define EN7581_CLK_EMMC 8
-+
- #endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */
projects / thirdparty / openwrt.git / commitdiff
