drm/tidss: Add simple K2G manual reset

[ Upstream commit 576d96c5c896221b5bc8feae473739469a92e144 ]

K2G display controller does not support soft reset, but we can do the
most important steps manually: mask the IRQs and disable the VPs.

Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com>
Link: https://lore.kernel.org/r/20231109-tidss-probe-v2-7-ac91b5ea35c0@ideasonboard.com
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Stable-dep-of: a9a73f2661e6 ("drm/tidss: Fix race condition while handling interrupt registers")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index c986d432af5071d18bf0526db8900b682fea7073..d3e57e6de5dbbf8e810e95b247b031a32a81c49b 100644 (file)
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -2655,14 +2655,28 @@ static void dispc_init_errata(struct dispc_device *dispc)
        }
 }
 
+/*
+ * K2G display controller does not support soft reset, so we do a basic manual
+ * reset here: make sure the IRQs are masked and VPs are disabled.
+ */
+static void dispc_softreset_k2g(struct dispc_device *dispc)
+{
+       dispc_set_irqenable(dispc, 0);
+       dispc_read_and_clear_irqstatus(dispc);
+
+       for (unsigned int vp_idx = 0; vp_idx < dispc->feat->num_vps; ++vp_idx)
+               VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, 0, 0);
+}
+
 static int dispc_softreset(struct dispc_device *dispc)
 {
        u32 val;
        int ret = 0;
 
-       /* K2G display controller does not support soft reset */
-       if (dispc->feat->subrev == DISPC_K2G)
+       if (dispc->feat->subrev == DISPC_K2G) {
+               dispc_softreset_k2g(dispc);
                return 0;
+       }
 
        /* Soft reset */
        REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1);