/* -------------- */
pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] if G bit is set. Must be set to 0x2 if G bit is cleared. */
/* -------------- */
-};
+};
/* Send doorbell */
pseudo_bit_t reserved1[0x00002];
pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */
/* -------------- */
-};
+};
/* ACCESS_LAM_inject_errors_input_modifier */
pseudo_bit_t index0[0x00007];
pseudo_bit_t q0[0x00001];
/* -------------- */
-};
+};
/* ACCESS_LAM_inject_errors_input_parameter */
pseudo_bit_t ra[0x00010]; /* Row Address */
pseudo_bit_t ca[0x00010]; /* Column Address */
/* -------------- */
-};
+};
/* */
*/
pseudo_bit_t reserved1[0x0001a];
/* -------------- */
-};
+};
/* Send wqe segment data inline */
/* -------------- */
pseudo_bit_t reserved2[0x00040];
/* -------------- */
-};
+};
/* Send wqe segment data ptr */
/* -------------- */
pseudo_bit_t local_address_l[0x00020];
/* -------------- */
-};
+};
/* Send wqe segment rd */
/* -------------- */
pseudo_bit_t reserved2[0x000a0];
/* -------------- */
-};
+};
/* Fast_Registration_Segment */
/* -------------- */
pseudo_bit_t reg_len_l[0x00020]; /* Region Length[31:0] */
/* -------------- */
-};
+};
/* Send wqe segment atomic */
/* -------------- */
pseudo_bit_t compare_l[0x00020];
/* -------------- */
-};
+};
/* Send wqe segment remote address */
/* -------------- */
pseudo_bit_t reserved0[0x00020];
/* -------------- */
-};
+};
/* end wqe segment bind */
/* -------------- */
pseudo_bit_t length_l[0x00020];
/* -------------- */
-};
+};
/* Send wqe segment ud */
/* -------------- */
pseudo_bit_t reserved1[0x00040];
/* -------------- */
-};
+};
/* Send wqe segment rd */
/* -------------- */
pseudo_bit_t reserved1[0x00040];
/* -------------- */
-};
+};
/* Send wqe segment ctrl */
/* -------------- */
pseudo_bit_t immediate[0x00020]; /* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */
/* -------------- */
-};
+};
/* Send wqe segment next */
pseudo_bit_t always1[0x00001];
pseudo_bit_t reserved1[0x00018];
/* -------------- */
-};
+};
/* Address Path */
/* -------------- */
pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */
/* -------------- */
-};
+};
/* HCA Command Register (HCR) */
pseudo_bit_t status[0x00008]; /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared)
0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */
/* -------------- */
-};
+};
/* CQ Doorbell */
/* -------------- */
pseudo_bit_t cq_param[0x00020]; /* parameter to be used by CQ command */
/* -------------- */
-};
+};
/* RD-send doorbell */
/* -------------- */
struct arbelprm_send_doorbell_st send_doorbell;/* Send Parameters */
/* -------------- */
-};
+};
/* Multicast Group Member QP */
pseudo_bit_t reserved0[0x00007];
pseudo_bit_t qi[0x00001]; /* Qi: QPN_i is valid */
/* -------------- */
-};
+};
/* vsd */
/* -------------- */
pseudo_bit_t vsd_dw55[0x00020];
/* -------------- */
-};
+};
/* ACCESS_LAM_inject_errors */
/* -------------- */
pseudo_bit_t reserved0[0x00020];
/* -------------- */
-};
+};
/* Logical DIMM Information */
/* -------------- */
pseudo_bit_t reserved4[0x00040];
/* -------------- */
-};
+};
/* UAR Parameters */
Number of entries in table is 2^log_max_uars.
Table must be aligned to its size. */
/* -------------- */
-};
+};
/* Translation and Protection Tables Parameters */
/* -------------- */
pseudo_bit_t reserved3[0x00040];
/* -------------- */
-};
+};
/* Multicast Support Parameters */
/* -------------- */
pseudo_bit_t reserved5[0x00020];
/* -------------- */
-};
+};
/* QPC/EEC/CQC/EQC/RDB Parameters */
/* -------------- */
pseudo_bit_t reserved10[0x00040];
/* -------------- */
-};
+};
/* Header_Log_Register */
/* -------------- */
pseudo_bit_t reserved0[0x00060];
/* -------------- */
-};
+};
/* Performance Monitors */
/* -------------- */
pseudo_bit_t event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */
/* -------------- */
-};
+};
/* Receive segment format */
/* -------------- */
pseudo_bit_t reserved4[0x00020];
/* -------------- */
-};
+};
/* MLX WQE segment format */
pseudo_bit_t vcrc[0x00010]; /* Packet's VCRC (if not 0 - otherwise computed by HW) */
pseudo_bit_t rlid[0x00010]; /* Destination LID (must match given headers) */
/* -------------- */
-};
+};
/* Send WQE segment format */
/* -------------- */
pseudo_bit_t reserved1[0x00200];
/* -------------- */
-};
+};
/* QP and EE Context Entry */
/* -------------- */
pseudo_bit_t reserved33[0x00040];
/* -------------- */
-};
+};
/* Clear Interrupt [63:0] */
Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot.
This register is write-only. Reading from this register will cause undefined result */
/* -------------- */
-};
+};
/* EQ_Arm_DB_Region */
pseudo_bit_t eq_x_arm_l[0x00020]; /* EQ[31:0] X state.
This register is used to Arm EQs when setting the appropriate bits. */
/* -------------- */
-};
+};
/* EQ Set CI DBs Table */
/* -------------- */
pseudo_bit_t reserved63[0x00020];
/* -------------- */
-};
+};
/* InfiniHost-III-EX Configuration Registers */
/* -------------- */
pseudo_bit_t reserved1[0x3fcb20];
/* -------------- */
-};
+};
/* QP_DB_Record */
0x5 for SRQ */
pseudo_bit_t qp_number[0x00018]; /* QP number */
/* -------------- */
-};
+};
/* CQ_ARM_DB_Record */
pseudo_bit_t res[0x00003]; /* Must be 0x2 */
pseudo_bit_t cq_number[0x00018]; /* CQ number */
/* -------------- */
-};
+};
/* CQ_CI_DB_Record */
pseudo_bit_t res[0x00003]; /* Must be 0x1 */
pseudo_bit_t cq_number[0x00018]; /* CQ number */
/* -------------- */
-};
+};
/* Virtual_Physical_Mapping */
pseudo_bit_t reserved1[0x00006];
pseudo_bit_t pa_l[0x00014]; /* Physical Address[31:12] */
/* -------------- */
-};
+};
/* MOD_STAT_CFG */
/* -------------- */
pseudo_bit_t reserved2[0x007e0];
/* -------------- */
-};
+};
/* SRQ Context */
/* -------------- */
pseudo_bit_t reserved4[0x00060];
/* -------------- */
-};
+};
/* PBL */
/* -------------- */
pseudo_bit_t mtt_3_l[0x00020]; /* Fourth MTT[31:0] */
/* -------------- */
-};
+};
/* Performance Counters */
/* -------------- */
pseudo_bit_t reserved3[0x00620];
/* -------------- */
-};
+};
/* Transport and CI Error Counters */
/* -------------- */
pseudo_bit_t reserved12[0x002a0];
/* -------------- */
-};
+};
/* Event_data Field - HCR Completion Event */
/* -------------- */
pseudo_bit_t reserved3[0x00020];
/* -------------- */
-};
+};
/* Completion with Error CQE */
0xFE - For completion with error on Receive Queues
0xFF - For completion with error on Send Queues */
/* -------------- */
-};
+};
/* Resize CQ Input Mailbox */
/* -------------- */
pseudo_bit_t reserved4[0x00100];
/* -------------- */
-};
+};
/* MAD_IFC Input Modifier */
pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD.
This field is required for trap generation upon MKey/BKey validation. */
/* -------------- */
-};
+};
/* MAD_IFC Input Mailbox */
/* -------------- */
pseudo_bit_t reserved5[0x004c0];
/* -------------- */
-};
+};
/* Query Debug Message */
/* -------------- */
pseudo_bit_t reserved3[0x00400];
/* -------------- */
-};
+};
/* User Access Region */
/* -------------- */
pseudo_bit_t reserved1[0x03ec0];
/* -------------- */
-};
+};
/* Receive doorbell */
pseudo_bit_t reserved3[0x00002];
pseudo_bit_t qpn[0x00018]; /* QP number or SRQ number this doorbell is rung on */
/* -------------- */
-};
+};
/* SET_IB Parameters */
/* -------------- */
pseudo_bit_t reserved2[0x00180];
/* -------------- */
-};
+};
/* Multicast Group Member */
/* -------------- */
struct arbelprm_mgmqp_st mgmqp_7; /* Multicast Group Member QP */
/* -------------- */
-};
+};
/* INIT_IB Parameters */
/* -------------- */
pseudo_bit_t reserved5[0x006c0];
/* -------------- */
-};
+};
/* Query Device Limitations */
/* -------------- */
pseudo_bit_t reserved41[0x002c0];
/* -------------- */
-};
+};
/* QUERY_ADAPTER Parameters Block */
/* -------------- */
struct arbelprm_vsd_st vsd;
/* -------------- */
-};
+};
/* QUERY_FW Parameters Block */
/* -------------- */
pseudo_bit_t reserved6[0x004c0];
/* -------------- */
-};
+};
/* ACCESS_LAM */
/* -------------- */
pseudo_bit_t reserved0[0x00080];
/* -------------- */
-};
+};
/* ENABLE_LAM Parameters Block */
/* -------------- */
pseudo_bit_t reserved2[0x00400];
/* -------------- */
-};
+};
/* Memory Access Parameters for UD Address Vector Table */
pseudo_bit_t xlation_en[0x00001]; /* When cleared, address is physical address and no translation will be done. When set, address is virtual. */
pseudo_bit_t reserved1[0x00002];
/* -------------- */
-};
+};
/* INIT_HCA & QUERY_HCA Parameters Block */
/* -------------- */
pseudo_bit_t reserved11[0x00600];
/* -------------- */
-};
+};
/* Event Queue Context Table Entry */
/* -------------- */
pseudo_bit_t reserved9[0x00080];
/* -------------- */
-};
+};
/* Memory Translation Table (MTT) Entry */
pseudo_bit_t reserved0[0x0000b];
pseudo_bit_t ptag_l[0x00014]; /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
/* -------------- */
-};
+};
/* Memory Protection Table (MPT) Entry */
/* -------------- */
pseudo_bit_t reserved8[0x00040];
/* -------------- */
-};
+};
/* Completion Queue Context Table Entry */
/* -------------- */
pseudo_bit_t reserved8[0x00020];
/* -------------- */
-};
+};
/* GPIO_event_data */
/* -------------- */
pseudo_bit_t reserved1[0x00020];
/* -------------- */
-};
+};
/* Event_data Field - QP/EE Events */
/* -------------- */
pseudo_bit_t reserved4[0x00060];
/* -------------- */
-};
+};
/* InfiniHost-III-EX Type0 Configuration Header */
/* -------------- */
pseudo_bit_t reserved13[0x006a0];
/* -------------- */
-};
+};
/* Event Data Field - Performance Monitor */
/* -------------- */
pseudo_bit_t reserved1[0x00040];
/* -------------- */
-};
+};
/* Event_data Field - Page Faults */
/* -------------- */
pseudo_bit_t prefetch_len[0x00020]; /* Indicates how many subsequent pages in the same memory region/window will be accessed by the following transaction after this page fault is resolved. measured in bytes. SW can use this information in order to page-in the subsequent pages if they are not present. */
/* -------------- */
-};
+};
/* WQE segments format */
/* -------------- */
pseudo_bit_t reserved2[0x00080];
/* -------------- */
-};
+};
/* Event_data Field - Port State Change */
/* -------------- */
pseudo_bit_t reserved3[0x00060];
/* -------------- */
-};
+};
/* Event_data Field - Completion Queue Error */
/* -------------- */
pseudo_bit_t reserved3[0x00060];
/* -------------- */
-};
+};
/* Event_data Field - Completion Event */
/* -------------- */
pseudo_bit_t reserved1[0x000a0];
/* -------------- */
-};
+};
/* Event Queue Entry */
1 HW */
pseudo_bit_t reserved3[0x00018];
/* -------------- */
-};
+};
/* QP/EE State Transitions Command Parameters */
/* -------------- */
pseudo_bit_t reserved1[0x009c0];
/* -------------- */
-};
+};
/* Completion Queue Entry Format */
0xFE - For completion with error on Receive Queues
0xFF - For completion with error on Send Queues */
/* -------------- */
-};
+};
/* */
pseudo_bit_t err_ra[0x00010];
pseudo_bit_t err_ca[0x00010];
/* -------------- */
-};
+};
/* Event_data Field - ECC Detection Event */
pseudo_bit_t err_ra[0x00010]; /* Error row address */
pseudo_bit_t err_ca[0x00010]; /* Error column address */
/* -------------- */
-};
+};
/* Miscellaneous Counters */
/* -------------- */
pseudo_bit_t reserved0[0x007e0];
/* -------------- */
-};
+};
/* LAM_EN Output Parameter */
struct arbelprm_lam_en_out_param_st { /* Little Endian */
pseudo_bit_t reserved0[0x00040];
/* -------------- */
-};
+};
/* Extended_Completion_Queue_Entry */
struct arbelprm_extended_completion_queue_entry_st { /* Little Endian */
pseudo_bit_t reserved0[0x00020];
/* -------------- */
-};
+};
/* */
struct arbelprm_eq_cmd_doorbell_st { /* Little Endian */
pseudo_bit_t reserved0[0x00020];
/* -------------- */
-};
+};
/* 0 */
/* -------------- */
pseudo_bit_t reserved59[0xffcfc0];
/* -------------- */
-};
+};
#endif /* H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H */
projects / thirdparty / ipxe.git / commitdiff
